| リビジョン | 4d446a8134e0599b4b4a4faab1b5e8d8a8fddd81 (tree) |
|---|---|
| 日時 | 2019-11-18 23:21:58 |
| 作者 | Yoshinori Sato <ysato@user...> |
| コミッター | Yoshinori Sato |
update configuration.
arch/h8300/Kconfig (diff) arch/h8300/dts/edosk2674.dts (diff)
include/configs/edosk2674.h (diff)| @@ -44,10 +44,6 @@ config SYS_CPU | ||
| 44 | 44 | config CPU_H83069 |
| 45 | 45 | bool |
| 46 | 46 | |
| 47 | -config TIMER_BASE | |
| 48 | - hex | |
| 49 | - default 0xffff80 | |
| 50 | - | |
| 51 | 47 | source "board/h8300h_sim/Kconfig" |
| 52 | 48 | source "board/h8300s_sim/Kconfig" |
| 53 | 49 | source "board/ae3069/Kconfig" |
| @@ -6,7 +6,7 @@ | ||
| 6 | 6 | interrupt-parent = <&h8intc>; |
| 7 | 7 | |
| 8 | 8 | chosen { |
| 9 | - stdout-path = &sci0; | |
| 9 | + stdout-path = &sci2; | |
| 10 | 10 | }; |
| 11 | 11 | aliases { |
| 12 | 12 | serial0 = &sci0; |
| @@ -20,27 +20,23 @@ | ||
| 20 | 20 | clock-frequency = <33333333>; |
| 21 | 21 | clock-output-names = "xtal"; |
| 22 | 22 | }; |
| 23 | - pllclk: pllclk { | |
| 24 | - compatible = "renesas,h8s2678-pll-clock"; | |
| 25 | - clocks = <&xclk>; | |
| 26 | - #clock-cells = <0>; | |
| 27 | - reg = <0xfee03b 2>, <0xfee045 2>; | |
| 28 | - }; | |
| 29 | - core_clk: core_clk { | |
| 30 | - compatible = "renesas,h8300-div-clock"; | |
| 31 | - clocks = <&pllclk>; | |
| 32 | - #clock-cells = <0>; | |
| 33 | - reg = <0xfee03b 2>; | |
| 34 | - renesas,width = <3>; | |
| 35 | - }; | |
| 36 | 23 | fclk: fclk { |
| 37 | 24 | compatible = "fixed-factor-clock"; |
| 38 | - clocks = <&core_clk>; | |
| 25 | + clocks = <&xclk>; | |
| 39 | 26 | #clock-cells = <0>; |
| 40 | 27 | clock-div = <1>; |
| 41 | 28 | clock-mult = <1>; |
| 42 | 29 | }; |
| 43 | 30 | |
| 31 | + flash@0x0 { | |
| 32 | + compatible = "cfi-flash"; | |
| 33 | + reg = <0x00000000 0x04000000>; | |
| 34 | + bank-width = <2>; | |
| 35 | + device-width = <1>; | |
| 36 | + #address-cells = <1>; | |
| 37 | + #size-cells = <1>; | |
| 38 | + }; | |
| 39 | + | |
| 44 | 40 | memory@400000 { |
| 45 | 41 | device_type = "memory"; |
| 46 | 42 | reg = <0x400000 0x800000>; |
| @@ -100,5 +96,6 @@ | ||
| 100 | 96 | lan91c96: ethernet@f80000 { |
| 101 | 97 | compatible = "smsc,lan91c96"; |
| 102 | 98 | reg = <0xf80000 32>; |
| 99 | + lan91c96,bus = <8>; | |
| 103 | 100 | }; |
| 104 | 101 | }; |
| @@ -64,17 +64,11 @@ | ||
| 64 | 64 | |
| 65 | 65 | /* Board Clock */ |
| 66 | 66 | #define CONFIG_SYS_CLK_FREQ 33333333 |
| 67 | -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
| 68 | 67 | #define CONFIG_SYS_HZ 1000 |
| 69 | 68 | |
| 70 | -#ifdef CONFIG_CMD_NET | |
| 71 | -/* Ether */ | |
| 72 | -#define CONFIG_LAN91C96 1 | |
| 73 | -#define CONFIG_LAN91C96_BASE 0xf80000 | |
| 74 | -#endif | |
| 75 | - | |
| 76 | 69 | /* Flash */ |
| 77 | 70 | #define CONFIG_SYS_FLASH_BASE EDOSK2674_FLASH_BASE |
| 78 | - | |
| 71 | +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 | |
| 72 | +#define CONFIG_SYS_FLASH_CFI 1 | |
| 79 | 73 | |
| 80 | 74 | #endif /* __EDOSK2674_H */ |
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