リビジョン | eef11ce325f1544ca0cafb1c734cdb8b1d0cb123 (tree) |
---|---|
日時 | 2022-01-21 14:52:57 |
作者 | LIU Zhiwei <zhiwei_liu@c-sk...> |
コミッター | Alistair Francis |
target/riscv: Remove VILL field in VTYPE
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-18-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
@@ -111,7 +111,6 @@ FIELD(VTYPE, VTA, 6, 1) | ||
111 | 111 | FIELD(VTYPE, VMA, 7, 1) |
112 | 112 | FIELD(VTYPE, VEDIV, 8, 2) |
113 | 113 | FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) |
114 | -FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) | |
115 | 114 | |
116 | 115 | struct CPURISCVState { |
117 | 116 | target_ulong gpr[32]; |