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コミットメタ情報

リビジョンa332a4023026571123ce8c36077da07e6397edd2 (tree)
日時2019-10-14 20:30:11
作者Yoshinori Sato <ysato@user...>
コミッターYoshinori Sato

ログメッセージ

hw/char: RX62N serial communication interface (SCI)

This module supported only non FIFO type.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20190607091116.49044-8-ysato@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

変更サマリ

差分

--- a/hw/char/Kconfig
+++ b/hw/char/Kconfig
@@ -46,3 +46,6 @@ config SCLPCONSOLE
4646
4747 config TERMINAL3270
4848 bool
49+
50+config RENESAS_SCI
51+ bool
--- a/hw/char/Makefile.objs
+++ b/hw/char/Makefile.objs
@@ -21,6 +21,7 @@ obj-$(CONFIG_PSERIES) += spapr_vty.o
2121 obj-$(CONFIG_DIGIC) += digic-uart.o
2222 obj-$(CONFIG_STM32F2XX_USART) += stm32f2xx_usart.o
2323 obj-$(CONFIG_RASPI) += bcm2835_aux.o
24+obj-$(CONFIG_RENESAS_SCI) += renesas_sci.o
2425
2526 common-obj-$(CONFIG_CMSDK_APB_UART) += cmsdk-apb-uart.o
2627 common-obj-$(CONFIG_ETRAXFS) += etraxfs_ser.o
--- /dev/null
+++ b/hw/char/renesas_sci.c
@@ -0,0 +1,343 @@
1+/*
2+ * Renesas Serial Communication Interface
3+ *
4+ * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware
5+ * (Rev.1.40 R01UH0033EJ0140)
6+ *
7+ * Copyright (c) 2019 Yoshinori Sato
8+ *
9+ * This program is free software; you can redistribute it and/or modify it
10+ * under the terms and conditions of the GNU General Public License,
11+ * version 2 or later, as published by the Free Software Foundation.
12+ *
13+ * This program is distributed in the hope it will be useful, but WITHOUT
14+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16+ * more details.
17+ *
18+ * You should have received a copy of the GNU General Public License along with
19+ * this program. If not, see <http://www.gnu.org/licenses/>.
20+ */
21+
22+#include "qemu/osdep.h"
23+#include "qemu/log.h"
24+#include "qapi/error.h"
25+#include "qemu-common.h"
26+#include "cpu.h"
27+#include "hw/hw.h"
28+#include "hw/irq.h"
29+#include "hw/sysbus.h"
30+#include "hw/registerfields.h"
31+#include "hw/qdev-properties.h"
32+#include "hw/char/renesas_sci.h"
33+#include "migration/vmstate.h"
34+#include "qemu/error-report.h"
35+
36+/* SCI register map */
37+REG8(SMR, 0)
38+ FIELD(SMR, CKS, 0, 2)
39+ FIELD(SMR, MP, 2, 1)
40+ FIELD(SMR, STOP, 3, 1)
41+ FIELD(SMR, PM, 4, 1)
42+ FIELD(SMR, PE, 5, 1)
43+ FIELD(SMR, CHR, 6, 1)
44+ FIELD(SMR, CM, 7, 1)
45+REG8(BRR, 1)
46+REG8(SCR, 2)
47+ FIELD(SCR, CKE, 0, 2)
48+ FIELD(SCR, TEIE, 2, 1)
49+ FIELD(SCR, MPIE, 3, 1)
50+ FIELD(SCR, RE, 4, 1)
51+ FIELD(SCR, TE, 5, 1)
52+ FIELD(SCR, RIE, 6, 1)
53+ FIELD(SCR, TIE, 7, 1)
54+REG8(TDR, 3)
55+REG8(SSR, 4)
56+ FIELD(SSR, MPBT, 0, 1)
57+ FIELD(SSR, MPB, 1, 1)
58+ FIELD(SSR, TEND, 2, 1)
59+ FIELD(SSR, ERR, 3, 3)
60+ FIELD(SSR, PER, 3, 1)
61+ FIELD(SSR, FER, 4, 1)
62+ FIELD(SSR, ORER, 5, 1)
63+ FIELD(SSR, RDRF, 6, 1)
64+ FIELD(SSR, TDRE, 7, 1)
65+REG8(RDR, 5)
66+REG8(SCMR, 6)
67+ FIELD(SCMR, SMIF, 0, 1)
68+ FIELD(SCMR, SINV, 2, 1)
69+ FIELD(SCMR, SDIR, 3, 1)
70+ FIELD(SCMR, BCP2, 7, 1)
71+REG8(SEMR, 7)
72+ FIELD(SEMR, ACS0, 0, 1)
73+ FIELD(SEMR, ABCS, 4, 1)
74+
75+static int can_receive(void *opaque)
76+{
77+ RSCIState *sci = RSCI(opaque);
78+ if (sci->rx_next > qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
79+ return 0;
80+ } else {
81+ return FIELD_EX8(sci->scr, SCR, RE);
82+ }
83+}
84+
85+static void receive(void *opaque, const uint8_t *buf, int size)
86+{
87+ RSCIState *sci = RSCI(opaque);
88+ sci->rx_next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + sci->trtime;
89+ if (FIELD_EX8(sci->ssr, SSR, RDRF) || size > 1) {
90+ sci->ssr = FIELD_DP8(sci->ssr, SSR, ORER, 1);
91+ if (FIELD_EX8(sci->scr, SCR, RIE)) {
92+ qemu_set_irq(sci->irq[ERI], 1);
93+ }
94+ } else {
95+ sci->rdr = buf[0];
96+ sci->ssr = FIELD_DP8(sci->ssr, SSR, RDRF, 1);
97+ if (FIELD_EX8(sci->scr, SCR, RIE)) {
98+ qemu_irq_pulse(sci->irq[RXI]);
99+ }
100+ }
101+}
102+
103+static void send_byte(RSCIState *sci)
104+{
105+ if (qemu_chr_fe_backend_connected(&sci->chr)) {
106+ qemu_chr_fe_write_all(&sci->chr, &sci->tdr, 1);
107+ }
108+ timer_mod(sci->timer,
109+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + sci->trtime);
110+ sci->ssr = FIELD_DP8(sci->ssr, SSR, TEND, 0);
111+ sci->ssr = FIELD_DP8(sci->ssr, SSR, TDRE, 1);
112+ qemu_set_irq(sci->irq[TEI], 0);
113+ if (FIELD_EX8(sci->scr, SCR, TIE)) {
114+ qemu_irq_pulse(sci->irq[TXI]);
115+ }
116+}
117+
118+static void txend(void *opaque)
119+{
120+ RSCIState *sci = RSCI(opaque);
121+ if (!FIELD_EX8(sci->ssr, SSR, TDRE)) {
122+ send_byte(sci);
123+ } else {
124+ sci->ssr = FIELD_DP8(sci->ssr, SSR, TEND, 1);
125+ if (FIELD_EX8(sci->scr, SCR, TEIE)) {
126+ qemu_set_irq(sci->irq[TEI], 1);
127+ }
128+ }
129+}
130+
131+static void update_trtime(RSCIState *sci)
132+{
133+ /* char per bits */
134+ sci->trtime = 8 - FIELD_EX8(sci->smr, SMR, CHR);
135+ sci->trtime += FIELD_EX8(sci->smr, SMR, PE);
136+ sci->trtime += FIELD_EX8(sci->smr, SMR, STOP) + 1;
137+ /* x bit transmit time (32 * divrate * brr) / base freq */
138+ sci->trtime *= 32 * sci->brr;
139+ sci->trtime *= 1 << (2 * FIELD_EX8(sci->smr, SMR, CKS));
140+ sci->trtime *= NANOSECONDS_PER_SECOND;
141+ sci->trtime /= sci->input_freq;
142+}
143+
144+#define IS_TR_ENABLED(scr) \
145+ (FIELD_EX8(scr, SCR, TE) || FIELD_EX8(scr, SCR, RE))
146+
147+static void sci_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
148+{
149+ hwaddr offset = addr & 0x07;
150+ RSCIState *sci = RSCI(opaque);
151+
152+ switch (offset) {
153+ case A_SMR:
154+ if (!IS_TR_ENABLED(sci->scr)) {
155+ sci->smr = val;
156+ update_trtime(sci);
157+ }
158+ break;
159+ case A_BRR:
160+ if (!IS_TR_ENABLED(sci->scr)) {
161+ sci->brr = val;
162+ update_trtime(sci);
163+ }
164+ break;
165+ case A_SCR:
166+ sci->scr = val;
167+ if (FIELD_EX8(sci->scr, SCR, TE)) {
168+ sci->ssr = FIELD_DP8(sci->ssr, SSR, TDRE, 1);
169+ sci->ssr = FIELD_DP8(sci->ssr, SSR, TEND, 1);
170+ if (FIELD_EX8(sci->scr, SCR, TIE)) {
171+ qemu_irq_pulse(sci->irq[TXI]);
172+ }
173+ }
174+ if (!FIELD_EX8(sci->scr, SCR, TEIE)) {
175+ qemu_set_irq(sci->irq[TEI], 0);
176+ }
177+ if (!FIELD_EX8(sci->scr, SCR, RIE)) {
178+ qemu_set_irq(sci->irq[ERI], 0);
179+ }
180+ break;
181+ case A_TDR:
182+ sci->tdr = val;
183+ if (FIELD_EX8(sci->ssr, SSR, TEND)) {
184+ send_byte(sci);
185+ } else {
186+ sci->ssr = FIELD_DP8(sci->ssr, SSR, TDRE, 0);
187+ }
188+ break;
189+ case A_SSR:
190+ sci->ssr = FIELD_DP8(sci->ssr, SSR, MPBT,
191+ FIELD_EX8(val, SSR, MPBT));
192+ sci->ssr = FIELD_DP8(sci->ssr, SSR, ERR,
193+ FIELD_EX8(val, SSR, ERR) & 0x07);
194+ if (FIELD_EX8(sci->read_ssr, SSR, ERR) &&
195+ FIELD_EX8(sci->ssr, SSR, ERR) == 0) {
196+ qemu_set_irq(sci->irq[ERI], 0);
197+ }
198+ break;
199+ case A_RDR:
200+ qemu_log_mask(LOG_GUEST_ERROR, "reneas_sci: RDR is read only.\n");
201+ break;
202+ case A_SCMR:
203+ sci->scmr = val; break;
204+ case A_SEMR: /* SEMR */
205+ sci->semr = val; break;
206+ default:
207+ qemu_log_mask(LOG_UNIMP, "renesas_sci: Register 0x%" HWADDR_PRIX
208+ " not implemented\n", offset);
209+ }
210+}
211+
212+static uint64_t sci_read(void *opaque, hwaddr addr, unsigned size)
213+{
214+ hwaddr offset = addr & 0x07;
215+ RSCIState *sci = RSCI(opaque);
216+
217+ switch (offset) {
218+ case A_SMR:
219+ return sci->smr;
220+ case A_BRR:
221+ return sci->brr;
222+ case A_SCR:
223+ return sci->scr;
224+ case A_TDR:
225+ return sci->tdr;
226+ case A_SSR:
227+ sci->read_ssr = sci->ssr;
228+ return sci->ssr;
229+ case A_RDR:
230+ sci->ssr = FIELD_DP8(sci->ssr, SSR, RDRF, 0);
231+ return sci->rdr;
232+ case A_SCMR:
233+ return sci->scmr;
234+ case A_SEMR:
235+ return sci->semr;
236+ default:
237+ qemu_log_mask(LOG_UNIMP, "renesas_sci: Register 0x%" HWADDR_PRIX
238+ " not implemented.\n", offset);
239+ }
240+ return UINT64_MAX;
241+}
242+
243+static const MemoryRegionOps sci_ops = {
244+ .write = sci_write,
245+ .read = sci_read,
246+ .endianness = DEVICE_NATIVE_ENDIAN,
247+ .impl = {
248+ .max_access_size = 1,
249+ },
250+};
251+
252+static void rsci_reset(DeviceState *dev)
253+{
254+ RSCIState *sci = RSCI(dev);
255+ sci->smr = sci->scr = 0x00;
256+ sci->brr = 0xff;
257+ sci->tdr = 0xff;
258+ sci->rdr = 0x00;
259+ sci->ssr = 0x84;
260+ sci->scmr = 0x00;
261+ sci->semr = 0x00;
262+ sci->rx_next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
263+}
264+
265+static void sci_event(void *opaque, int event)
266+{
267+ RSCIState *sci = RSCI(opaque);
268+ if (event == CHR_EVENT_BREAK) {
269+ sci->ssr = FIELD_DP8(sci->ssr, SSR, FER, 1);
270+ if (FIELD_EX8(sci->scr, SCR, RIE)) {
271+ qemu_set_irq(sci->irq[ERI], 1);
272+ }
273+ }
274+}
275+
276+static void rsci_realize(DeviceState *dev, Error **errp)
277+{
278+ RSCIState *sci = RSCI(dev);
279+
280+ if (sci->input_freq == 0) {
281+ qemu_log_mask(LOG_GUEST_ERROR,
282+ "renesas_sci: input-freq property must be set.");
283+ return;
284+ }
285+ qemu_chr_fe_set_handlers(&sci->chr, can_receive, receive,
286+ sci_event, NULL, sci, NULL, true);
287+}
288+
289+static void rsci_init(Object *obj)
290+{
291+ SysBusDevice *d = SYS_BUS_DEVICE(obj);
292+ RSCIState *sci = RSCI(obj);
293+ int i;
294+
295+ memory_region_init_io(&sci->memory, OBJECT(sci), &sci_ops,
296+ sci, "renesas-sci", 0x8);
297+ sysbus_init_mmio(d, &sci->memory);
298+
299+ for (i = 0; i < SCI_NR_IRQ; i++) {
300+ sysbus_init_irq(d, &sci->irq[i]);
301+ }
302+ sci->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, txend, sci);
303+}
304+
305+static const VMStateDescription vmstate_rsci = {
306+ .name = "renesas-sci",
307+ .version_id = 1,
308+ .minimum_version_id = 1,
309+ .fields = (VMStateField[]) {
310+ VMSTATE_END_OF_LIST()
311+ }
312+};
313+
314+static Property rsci_properties[] = {
315+ DEFINE_PROP_UINT64("input-freq", RSCIState, input_freq, 0),
316+ DEFINE_PROP_CHR("chardev", RSCIState, chr),
317+ DEFINE_PROP_END_OF_LIST(),
318+};
319+
320+static void rsci_class_init(ObjectClass *klass, void *data)
321+{
322+ DeviceClass *dc = DEVICE_CLASS(klass);
323+
324+ dc->realize = rsci_realize;
325+ dc->props = rsci_properties;
326+ dc->vmsd = &vmstate_rsci;
327+ dc->reset = rsci_reset;
328+}
329+
330+static const TypeInfo rsci_info = {
331+ .name = TYPE_RENESAS_SCI,
332+ .parent = TYPE_SYS_BUS_DEVICE,
333+ .instance_size = sizeof(RSCIState),
334+ .instance_init = rsci_init,
335+ .class_init = rsci_class_init,
336+};
337+
338+static void rsci_register_types(void)
339+{
340+ type_register_static(&rsci_info);
341+}
342+
343+type_init(rsci_register_types)
--- /dev/null
+++ b/include/hw/char/renesas_sci.h
@@ -0,0 +1,45 @@
1+/*
2+ * Renesas Serial Communication Interface
3+ *
4+ * Copyright (c) 2018 Yoshinori Sato
5+ *
6+ * This code is licensed under the GPL version 2 or later.
7+ *
8+ */
9+
10+#include "chardev/char-fe.h"
11+#include "qemu/timer.h"
12+#include "hw/sysbus.h"
13+
14+#define TYPE_RENESAS_SCI "renesas-sci"
15+#define RSCI(obj) OBJECT_CHECK(RSCIState, (obj), TYPE_RENESAS_SCI)
16+
17+enum {
18+ ERI = 0,
19+ RXI = 1,
20+ TXI = 2,
21+ TEI = 3,
22+ SCI_NR_IRQ = 4,
23+};
24+
25+typedef struct {
26+ SysBusDevice parent_obj;
27+ MemoryRegion memory;
28+
29+ uint8_t smr;
30+ uint8_t brr;
31+ uint8_t scr;
32+ uint8_t tdr;
33+ uint8_t ssr;
34+ uint8_t rdr;
35+ uint8_t scmr;
36+ uint8_t semr;
37+
38+ uint8_t read_ssr;
39+ int64_t trtime;
40+ int64_t rx_next;
41+ QEMUTimer *timer;
42+ CharBackend chr;
43+ uint64_t input_freq;
44+ qemu_irq irq[SCI_NR_IRQ];
45+} RSCIState;