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コミットメタ情報

リビジョン79f26b3b951dd8eeec23d437c41f0944167ce44d (tree)
日時2022-01-21 14:52:57
作者LIU Zhiwei <zhiwei_liu@c-sk...>
コミッターAlistair Francis

ログメッセージ

target/riscv: Adjust pmpcfg access with mxl

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-2-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

変更サマリ

差分

--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1497,9 +1497,23 @@ static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
14971497 return RISCV_EXCP_NONE;
14981498 }
14991499
1500+static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index)
1501+{
1502+ /* TODO: RV128 restriction check */
1503+ if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {
1504+ return false;
1505+ }
1506+ return true;
1507+}
1508+
15001509 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
15011510 target_ulong *val)
15021511 {
1512+ uint32_t reg_index = csrno - CSR_PMPCFG0;
1513+
1514+ if (!check_pmp_reg_index(env, reg_index)) {
1515+ return RISCV_EXCP_ILLEGAL_INST;
1516+ }
15031517 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
15041518 return RISCV_EXCP_NONE;
15051519 }
@@ -1507,6 +1521,11 @@ static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
15071521 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
15081522 target_ulong val)
15091523 {
1524+ uint32_t reg_index = csrno - CSR_PMPCFG0;
1525+
1526+ if (!check_pmp_reg_index(env, reg_index)) {
1527+ return RISCV_EXCP_ILLEGAL_INST;
1528+ }
15101529 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
15111530 return RISCV_EXCP_NONE;
15121531 }
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -463,16 +463,11 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
463463 {
464464 int i;
465465 uint8_t cfg_val;
466+ int pmpcfg_nums = 2 << riscv_cpu_mxl(env);
466467
467468 trace_pmpcfg_csr_write(env->mhartid, reg_index, val);
468469
469- if ((reg_index & 1) && (sizeof(target_ulong) == 8)) {
470- qemu_log_mask(LOG_GUEST_ERROR,
471- "ignoring pmpcfg write - incorrect address\n");
472- return;
473- }
474-
475- for (i = 0; i < sizeof(target_ulong); i++) {
470+ for (i = 0; i < pmpcfg_nums; i++) {
476471 cfg_val = (val >> 8 * i) & 0xff;
477472 pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
478473 }
@@ -490,8 +485,9 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
490485 int i;
491486 target_ulong cfg_val = 0;
492487 target_ulong val = 0;
488+ int pmpcfg_nums = 2 << riscv_cpu_mxl(env);
493489
494- for (i = 0; i < sizeof(target_ulong); i++) {
490+ for (i = 0; i < pmpcfg_nums; i++) {
495491 val = pmp_read_cfg(env, (reg_index * 4) + i);
496492 cfg_val |= (val << (i * 8));
497493 }