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リビジョン4302bef9e17831902a7e7c8082cac1c8ed151759 (tree)
日時2022-01-21 14:52:57
作者LIU Zhiwei <zhiwei_liu@c-sk...>
コミッターAlistair Francis

ログメッセージ

target/riscv: Calculate address according to XLEN

Define one common function to compute a canonical address from a register
plus offset. Merge gen_pm_adjust_address into this function.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-14-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

変更サマリ

差分

--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -20,12 +20,11 @@
2020
2121 static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
2222 {
23- TCGv src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
23+ TCGv src1 = get_address(ctx, a->rs1, 0);
2424
2525 if (a->rl) {
2626 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
2727 }
28- src1 = gen_pm_adjust_address(ctx, src1);
2928 tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
3029 if (a->aq) {
3130 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
@@ -44,8 +43,7 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
4443 TCGLabel *l1 = gen_new_label();
4544 TCGLabel *l2 = gen_new_label();
4645
47- src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
48- src1 = gen_pm_adjust_address(ctx, src1);
46+ src1 = get_address(ctx, a->rs1, 0);
4947 tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
5048
5149 /*
@@ -83,10 +81,9 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
8381 MemOp mop)
8482 {
8583 TCGv dest = dest_gpr(ctx, a->rd);
86- TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
84+ TCGv src1 = get_address(ctx, a->rs1, 0);
8785 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
8886
89- src1 = gen_pm_adjust_address(ctx, src1);
9087 func(dest, src1, src2, ctx->mem_idx, mop);
9188
9289 gen_set_gpr(ctx, a->rd, dest);
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -25,14 +25,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
2525 REQUIRE_FPU;
2626 REQUIRE_EXT(ctx, RVD);
2727
28- addr = get_gpr(ctx, a->rs1, EXT_NONE);
29- if (a->imm) {
30- TCGv temp = temp_new(ctx);
31- tcg_gen_addi_tl(temp, addr, a->imm);
32- addr = temp;
33- }
34- addr = gen_pm_adjust_address(ctx, addr);
35-
28+ addr = get_address(ctx, a->rs1, a->imm);
3629 tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEUQ);
3730
3831 mark_fs_dirty(ctx);
@@ -46,16 +39,8 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
4639 REQUIRE_FPU;
4740 REQUIRE_EXT(ctx, RVD);
4841
49- addr = get_gpr(ctx, a->rs1, EXT_NONE);
50- if (a->imm) {
51- TCGv temp = temp_new(ctx);
52- tcg_gen_addi_tl(temp, addr, a->imm);
53- addr = temp;
54- }
55- addr = gen_pm_adjust_address(ctx, addr);
56-
42+ addr = get_address(ctx, a->rs1, a->imm);
5743 tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUQ);
58-
5944 return true;
6045 }
6146
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -31,14 +31,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
3131 REQUIRE_FPU;
3232 REQUIRE_EXT(ctx, RVF);
3333
34- addr = get_gpr(ctx, a->rs1, EXT_NONE);
35- if (a->imm) {
36- TCGv temp = temp_new(ctx);
37- tcg_gen_addi_tl(temp, addr, a->imm);
38- addr = temp;
39- }
40- addr = gen_pm_adjust_address(ctx, addr);
41-
34+ addr = get_address(ctx, a->rs1, a->imm);
4235 dest = cpu_fpr[a->rd];
4336 tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL);
4437 gen_nanbox_s(dest, dest);
@@ -54,16 +47,8 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
5447 REQUIRE_FPU;
5548 REQUIRE_EXT(ctx, RVF);
5649
57- addr = get_gpr(ctx, a->rs1, EXT_NONE);
58- if (a->imm) {
59- TCGv temp = tcg_temp_new();
60- tcg_gen_addi_tl(temp, addr, a->imm);
61- addr = temp;
62- }
63- addr = gen_pm_adjust_address(ctx, addr);
64-
50+ addr = get_address(ctx, a->rs1, a->imm);
6551 tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL);
66-
6752 return true;
6853 }
6954
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -226,14 +226,7 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
226226 static bool gen_load_tl(DisasContext *ctx, arg_lb *a, MemOp memop)
227227 {
228228 TCGv dest = dest_gpr(ctx, a->rd);
229- TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
230-
231- if (a->imm) {
232- TCGv temp = temp_new(ctx);
233- tcg_gen_addi_tl(temp, addr, a->imm);
234- addr = temp;
235- }
236- addr = gen_pm_adjust_address(ctx, addr);
229+ TCGv addr = get_address(ctx, a->rs1, a->imm);
237230
238231 tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
239232 gen_set_gpr(ctx, a->rd, dest);
@@ -330,16 +323,9 @@ static bool trans_ldu(DisasContext *ctx, arg_ldu *a)
330323
331324 static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop)
332325 {
333- TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
326+ TCGv addr = get_address(ctx, a->rs1, a->imm);
334327 TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
335328
336- if (a->imm) {
337- TCGv temp = temp_new(ctx);
338- tcg_gen_addi_tl(temp, addr, a->imm);
339- addr = temp;
340- }
341- addr = gen_pm_adjust_address(ctx, addr);
342-
343329 tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
344330 return true;
345331 }
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -390,21 +390,20 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
390390 ctx->base.is_jmp = DISAS_NORETURN;
391391 }
392392
393-/*
394- * Generates address adjustment for PointerMasking
395- */
396-static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
393+/* Compute a canonical address from a register plus offset. */
394+static TCGv get_address(DisasContext *ctx, int rs1, int imm)
397395 {
398- TCGv temp;
399- if (!s->pm_enabled) {
400- /* Load unmodified address */
401- return src;
402- } else {
403- temp = temp_new(s);
404- tcg_gen_andc_tl(temp, src, pm_mask);
405- tcg_gen_or_tl(temp, temp, pm_base);
406- return temp;
396+ TCGv addr = temp_new(ctx);
397+ TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
398+
399+ tcg_gen_addi_tl(addr, src1, imm);
400+ if (ctx->pm_enabled) {
401+ tcg_gen_and_tl(addr, addr, pm_mask);
402+ tcg_gen_or_tl(addr, addr, pm_base);
403+ } else if (get_xl(ctx) == MXL_RV32) {
404+ tcg_gen_ext32u_tl(addr, addr);
407405 }
406+ return addr;
408407 }
409408
410409 #ifndef CONFIG_USER_ONLY