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リビジョン4208dc7e9e6fe1bb7a0698eac31f44388046dc00 (tree)
日時2022-01-21 14:52:57
作者LIU Zhiwei <zhiwei_liu@c-sk...>
コミッターAlistair Francis

ログメッセージ

target/riscv: Split pm_enabled into mask and base

Use cached cur_pmmask and cur_pmbase to infer the
current PM mode.

This may decrease the TCG IR by one when pm_enabled
is true and pm_base_enabled is false.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-15-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

変更サマリ

差分

--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -448,7 +448,8 @@ FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2)
448448 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
449449 FIELD(TB_FLAGS, XL, 20, 2)
450450 /* If PointerMasking should be applied */
451-FIELD(TB_FLAGS, PM_ENABLED, 22, 1)
451+FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
452+FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
452453
453454 #ifdef TARGET_RISCV32
454455 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -97,27 +97,15 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
9797 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
9898 get_field(env->mstatus_hs, MSTATUS_VS));
9999 }
100- if (riscv_has_ext(env, RVJ)) {
101- int priv = flags & TB_FLAGS_PRIV_MMU_MASK;
102- bool pm_enabled = false;
103- switch (priv) {
104- case PRV_U:
105- pm_enabled = env->mmte & U_PM_ENABLE;
106- break;
107- case PRV_S:
108- pm_enabled = env->mmte & S_PM_ENABLE;
109- break;
110- case PRV_M:
111- pm_enabled = env->mmte & M_PM_ENABLE;
112- break;
113- default:
114- g_assert_not_reached();
115- }
116- flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled);
117- }
118100 #endif
119101
120102 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
103+ if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) {
104+ flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
105+ }
106+ if (env->cur_pmbase != 0) {
107+ flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
108+ }
121109
122110 *pflags = flags;
123111 }
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -108,7 +108,8 @@ typedef struct DisasContext {
108108 /* Space for 3 operands plus 1 extra for address computation. */
109109 TCGv temp[4];
110110 /* PointerMasking extension */
111- bool pm_enabled;
111+ bool pm_mask_enabled;
112+ bool pm_base_enabled;
112113 } DisasContext;
113114
114115 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -397,12 +398,14 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
397398 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
398399
399400 tcg_gen_addi_tl(addr, src1, imm);
400- if (ctx->pm_enabled) {
401+ if (ctx->pm_mask_enabled) {
401402 tcg_gen_and_tl(addr, addr, pm_mask);
402- tcg_gen_or_tl(addr, addr, pm_base);
403403 } else if (get_xl(ctx) == MXL_RV32) {
404404 tcg_gen_ext32u_tl(addr, addr);
405405 }
406+ if (ctx->pm_base_enabled) {
407+ tcg_gen_or_tl(addr, addr, pm_base);
408+ }
406409 return addr;
407410 }
408411
@@ -925,7 +928,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
925928 ctx->cs = cs;
926929 ctx->ntemp = 0;
927930 memset(ctx->temp, 0, sizeof(ctx->temp));
928- ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
931+ ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
932+ ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
929933 ctx->zero = tcg_constant_tl(0);
930934 }
931935