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コミットメタ情報

リビジョン0cff460de9e3417d248a5756b1cfbd9211657f94 (tree)
日時2022-01-21 14:52:57
作者LIU Zhiwei <zhiwei_liu@c-sk...>
コミッターAlistair Francis

ログメッセージ

target/riscv: Alloc tcg global for cur_pm[mask|base]

Replace the array of pm_mask/pm_base with scalar variables.
Remove the cached array value in DisasContext.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-13-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

変更サマリ

差分

--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -38,8 +38,8 @@ static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
3838 static TCGv load_res;
3939 static TCGv load_val;
4040 /* globals for PM CSRs */
41-static TCGv pm_mask[4];
42-static TCGv pm_base[4];
41+static TCGv pm_mask;
42+static TCGv pm_base;
4343
4444 #include "exec/gen-icount.h"
4545
@@ -109,8 +109,6 @@ typedef struct DisasContext {
109109 TCGv temp[4];
110110 /* PointerMasking extension */
111111 bool pm_enabled;
112- TCGv pm_mask;
113- TCGv pm_base;
114112 } DisasContext;
115113
116114 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -403,8 +401,8 @@ static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
403401 return src;
404402 } else {
405403 temp = temp_new(s);
406- tcg_gen_andc_tl(temp, src, s->pm_mask);
407- tcg_gen_or_tl(temp, temp, s->pm_base);
404+ tcg_gen_andc_tl(temp, src, pm_mask);
405+ tcg_gen_or_tl(temp, temp, pm_base);
408406 return temp;
409407 }
410408 }
@@ -929,10 +927,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
929927 ctx->ntemp = 0;
930928 memset(ctx->temp, 0, sizeof(ctx->temp));
931929 ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
932- int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK;
933- ctx->pm_mask = pm_mask[priv];
934- ctx->pm_base = pm_base[priv];
935-
936930 ctx->zero = tcg_constant_tl(0);
937931 }
938932
@@ -1050,19 +1044,9 @@ void riscv_translate_init(void)
10501044 "load_res");
10511045 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
10521046 "load_val");
1053-#ifndef CONFIG_USER_ONLY
10541047 /* Assign PM CSRs to tcg globals */
1055- pm_mask[PRV_U] =
1056- tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask");
1057- pm_base[PRV_U] =
1058- tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase");
1059- pm_mask[PRV_S] =
1060- tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask");
1061- pm_base[PRV_S] =
1062- tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase");
1063- pm_mask[PRV_M] =
1064- tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask");
1065- pm_base[PRV_M] =
1066- tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase");
1067-#endif
1048+ pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask),
1049+ "pmmask");
1050+ pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase),
1051+ "pmbase");
10681052 }