コミット: 87d119348dbdd8f7afe497e05a5883312ac349d7 - jmr6805break (git)

およそ20年前に、68HC05 の開発の練習に書いた車のブレイクライト・方向指示器コントローラです。

コミットメタ情報

• リビジョン: 87d119348dbdd8f7afe497e05a5883312ac349d7 (tree)
• 日時: 2013-07-08 21:52:31
• 作者: Joel Matthew Rees <reiisi@user...>
• コミッター: Joel Matthew Rees

ログメッセージ

Refactoring and cleaning up the brake lights and emergency flashers.

変更サマリ

• delete: TURNSIG.AS4 => TURNSIG.AS5

差分

--- a/TURNSIG.AS4
+++ b/TURNSIG.AS5
@@ -3,7 +3,7 @@
 
 * Electronic Turn Signal and Emergency Flasher Switch/Timer
 *       Version 1.00
-*       Implemented on the 68HC(7)05Kx
+*       Implemented on the 68HC705K1
 *       Assembled and tested on the M68HC705KICS
 *
 *       Copyright 1993 Joel Matthew Rees
@@ -11,11 +11,11 @@
 *       Permission granted in advance for strictly non-profit
 * educational use.  All other rights retained by the author.
 
-* Authored by Joel Matthew Rees, June to October 1993
-*       of
-*       South Salt Lake City
-*       Utah 
-*       
+* Authored by Joel Matthew Rees, June to November 1993
+*   of                                  also of
+*   South Salt Lake City                Amagasaki
+*   Utah                                Japan
+*   
 
 
 
@@ -54,7 +54,7 @@
 * program, but has not been tested in a physical mock up or real
 * vehicle.
 
-*       One of the objects of this design was to replace mechanical
+*       One of the intents of this design was to replace mechanical
 * parts (that tend to flow in hot climates and become brittle in cold)
 * with logic.  In order to eliminate the mechanical latching lever with
 * spring loaded return, I have (perhaps arbitrarily) enforced a new "user
@@ -213,7 +213,8 @@
 * manual cancel, the cancel port can sense steering wheel rotation.  In
 * same direction rotation, there is a lead period when the cancel input
 * does not remain high if the turn signal input ports' output states are
-* inverted.  Debounce suppresses cancel under these conditions.
+* inverted.  The debounce routine suppresses cancel under the latter
+* conditions.
 
 *       Since the opposite direction turn signal switch port remains an
 * input, it can still be sensed.  The operator can change turn signals
@@ -222,11 +223,11 @@
 *       The separation of the switches and the actuation arc length I
 * specify are based on my assumption that the steering wheel will rotate
 * at a maximum speed of three revolutions per second, and that the four
-* to six mS required debounce period requires a minimum 10 milli-second
-* separate actuation period.  The actual result was 10.9 degrees
-* separate actuation (21.8 total), which I arbitrarily rounded up to a
-* power of two fraction of the circle: 2*PI/16 total actuation and
-* 2*PI/32 separate actuation.
+* to six mS (1 MHz crystal) required debounce period requires a minimum
+* 10 milli-second separate actuation period.  The actual result was 10.9
+* degrees separate actuation (21.8 total), which I arbitrarily rounded
+* up to a power of two fraction of the circle: 2*PI/16 total actuation
+* and 2*PI/32 separate actuation.
 
 *       A peculiar characteristic of this design is the apparent lack of
 * use for the RESET input.  Since power-on reset is built in to the
@@ -235,7 +236,7 @@
 
 *       This assembler appears not to have a bit-not function for
 * operand expressions.  So, I have in several places resorted to the
-* rather obtuse expedient of exclusive-orring bits to be reset with $FF,
+* obtuse expedient of exclusive-orring bits to be reset with $FF,
 * ergo,                 AND #{$FF ^ F_OPC ^ F_MNC}
 * instead of            AND #~(F_OPC | F_MNC)
 * which I think would have been clearer.
@@ -257,11 +258,11 @@ R_LDRV  equ B5
 R_LDRV_ equ B5_
 R_RDRV  equ B4
 R_RDRV_ equ B4_
-ALLAMPS equ {F_LDRV | F_RDRV | R_LDRV | R_RDRV}
+DRVLMPS equ {F_LDRV | F_RDRV | R_LDRV | R_RDRV}
 LFTDRV  equ {F_LDRV | R_LDRV}
 RGTDRV  equ {F_RDRV | R_RDRV}
 FRNTDRV equ {F_LDRV | F_RDRV}
-REARDRV eau {R_LDRV | R_RDRV}
+REARDRV equ {R_LDRV | R_RDRV}
 BRK_SW  equ B3
 BRK_SW_ equ B3_
 NGN_SW  equ B2          ; engine (ENG and EMG could be confusing)
@@ -311,7 +312,15 @@ FLASH0  equ {32*XTAL/RTIRATE/4}         ; about 1/4 second off time
 FLASH1  equ {32*XTAL/RTIRATE/2}         ; about 1/2 second on time
 
         org MOR
-        fcb {PIN3 | RC | PIRQ | COPEN}
+* Software Pulldown is used.
+* Can't spare the third RC oscillator pin.
+* Set RC because we assume the cheap oscillator.
+* STOP must not convert to WAIT: saves power when engine off.
+* Assume Low Voltage Reset would be meaningless.
+* PA3 - PA0 interrupts are used to bring the chip up for brake, engine on.
+* Accept level sensitive interrupts, since IRQ is disabled immediately.
+* Assume COP might be useful here.
+        fcb {RC | PIRQ | LEVEL | COPEN}
 
         org RAMBEG
 DEBO    rmb 3   ; the debounce record chain
@@ -338,11 +347,11 @@ FLMASK  rmb 1   ; flash mask to communicate between BRK, EMG, and TRN
 
 *       The debounce routine translates the physical inputs to logical
 * inputs, maintains a record of the last three logical states sensed in
-* DEBO, debounces each input on three identical states, flags changes in
-* the debounced input in TOGGLE, and leaves the current debounced input
-* in ISTATE.  Since debouncing occurs on three identical states, the
-* debounce period is between two and three timer overflows -- 4 to 6 mS
-* with a 1 MHz crystal, 2 to 3 mS with a 2 MHz crystal.
+* DEBO, debounces (in parallel) each input on three identical states,
+* flags changes in the debounced input in TOGGLE, and leaves the current
+* debounced input in ISTATE.  Since debouncing occurs on three identical
+* states, the debounce period is between two and three timer overflows
+* -- 4 to 6 mS with a 1 MHz crystal, 2 to 3 mS with a 2 MHz crystal.
 
 *       This debounce technique works because we don't care what is
 * happening to the inputs between timer overflows, and because we assume
@@ -357,28 +366,52 @@ FLMASK  rmb 1   ; flash mask to communicate between BRK, EMG, and TRN
 
 *       After adding an event queue and checking the timing results, two
 * things became clear: there is plenty of time to handle all the changes
-* to STATES without a queue, and TOGGLE makes a sort of horizontal queue
-* anyway.  In other words, there is no reason to make the adjustments to
-* STATES asynchronous when there is plenty of headroom for synchronous
-* adjustments.  Moreover, the adjustments take less time than organizing
-* the button events in a queue.  (Darn!  I was kind of proud of that six
-* byte queue, and the shift technique for storing events into it.)
-
-*       The engine time-out counter resets on any activity on the engine
-* switch, emergency flashers, or brake lights.  This has the side effect
-* of allowing the turn signals to function with the engine off for five
-* minutes after the engine is shut off, or for five minutes after either
-* the brakes or emergency flashers are used.
+* to STATES without a queue, and TOGGLE makes a sort of horizontal
+* priority queue anyway.  In other words, there is no reason to make the
+* adjustments to STATES asynchronous when there is plenty of headroom
+* for synchronous adjustments.  Moreover, the adjustments take less time
+* than organizing the button events in a queue.  (Darn!  I was kind of
+* proud of that six byte queue, and the shift technique for storing
+* events into it.)
+
+*       The engine time-out counter communicates with the power down
+* routine via the STATES engine on (F_NGN) bit.  In other words, STATES
+* F_NGN bit is held off until the ISTATE F_NGN bit and the STATES F_EMG
+* and F_BRK bits have been inactive for five minutes.  (This perhaps
+* overloads the semantics of STATES F_NGN.)
+
+*       In the current design, the turn signals are not masked with the
+* ISTATE F_NGN bit, and so will function during the time-out period.
+* This "feature" can easily be corrected in the debounce routine.
+
+*       It should be relatively easy to add a turn signal time-out
+* counter to turn off the turn signals after the same turn signal has
+* been on an un-reasonable period, such as five or more minutes.
+* Such a time-out might negatively impact safety when attempting to turn
+* in backed-up traffic or onto a very busy highway, or when using the
+* turn signal to show a car parked for delivery, etc.  It also might
+* cause drivers to become even lazier.
 
 *       Both timers reset in such a manner as to be in a known state at
 * any time they are put into use.
 
-*       The emergency and turn signal signal flasher shares a single
+*       The single emergency and turn signal signal flasher uses a single
 * rate and duty cycle.
 
         SUBHEADER 'Timer Service Code -- Debounce and Toggle Filter'
         PAGE
 
+        swi     ; since we have a few unused ROM locations
+        swi
+        swi
+        swi
+        swi
+        swi
+        swi
+        swi
+        swi
+        swi
+        swi
         swi
 
 $CYCLE_ADDER_ON
@@ -393,10 +426,10 @@ TIMSRV  bset TOFR_,TSCR
 * read the static inputs, converting physical to logical
         lda PORTA
         and #{BRK_SW | NGN_SW | CAN_BT}         ; clears DRV_DRV
-        bih TMMEMG      ; invert EMG and fold it in
+        bih TMIEMG      ; invert EMG and fold it in
         ora #F_EMG
-TMMEMG  lsra    ; remap
-        lsra
+TMIEMG  lsla    ; remap
+        lsla
         sta DEBO
         lda PORTB       ; PB2-7 always read 0
         ora DEBO
@@ -406,33 +439,36 @@ TMMEMG  lsra    ; remap
 * (F_CAN & turn_sig_on) <=> read auxiliary flags
 * Assume that DDRB showing output means turn signal on and waiting
 * for cancel.
+
         bit #F_CAN      ; nothing at all without cancel
-        beq TMSTGL
+        beq TM0TURN
         ldx DDRB        ; meaningless if not waiting for cancel
-        beq TMSTGL
+        beq TM0TURN
 $CYCLE_ADDER_OFF
 $CYCLE_ADDER_ON
         txa
         eor #{LFT_BT | RGT_BT}  ; strobe other side
         sta PORTB       ; set output state first
         sta DDRB        ; handy output state, huh?
-        brset F_CAN_,PORTA,TM0000       ; F_CAN into carry
-TM0000  rora
-        clr DDRB        ; no strobe: manual cancel?
-        brset F_CAN_,PORTA,TM0001       ; F_CAN into carry again
-TM0001  rora
+        brset F_CAN_,PORTA,TMTBIT6      ; F_CAN into carry
+TMTBIT6 rora    ; carry into bit 7
+        clr DDRB        ; kill strobe: manual cancel?
+        brset F_CAN_,PORTA,TMTBIT7      ; F_CAN into carry again
+TMTBIT7 rora    ; carry into bit 7 again
         and #{F_OPC | F_MNC}
         ora DEBO
         sta DEBO
         stx PORTB       ; restore turn signal inputs
         stx DDRB
+TM0TURN equ *
+* leave A == DEBO
 $CYCLE_ADDER_OFF
 $CYCLE_ADDER_ON
 
 * debounce inputs, set flags in TOGGLE and ISTATE
 * STABLE_BITS = ~((DEBO[0] ^ DEBO[1]) | (DEBO[1] ^ DEBO[2]))
-*
-TMSTGL  eor DEBO+1
+* A == DEBO on entry
+        eor DEBO+1
         sta TOGGLE      ; re-use TOGGLE, TOGGLE not valid
         lda DEBO+1
         eor DEBO+2
@@ -452,16 +488,20 @@ TMSTGL  eor DEBO+1
         and SSTBLE      ; new states of bits that toggled
         ora ISTATE
         sta ISTATE      ; ISTATE now has current debounced inputs
+* leave A == ISTATE
 
 * filter out TOGGLE F_CAN if same direction
+* A == ISTATE on ENTRY
         bit #{F_OPC | F_MNC}    ; opposite direction or manual?
-        bne TMFFAL
+        bne TMF1CAN
         bclr F_CAN_,TOGGLE      ; same direction
+TMF1CAN equ *
+* leave A == ISTATE
 
 * filter out trailing edge of F_LFT, F_RGT, F_EMG, F_CAN in TOGGLE
 * also filter out auxiliary TOGGLEs in passing
-* assumes ISTATE still in A
-TMFFAL  ora #{F_NGN | F_BRK}    ; not filtered
+* ISTATE == A on entry
+        ora #{F_NGN | F_BRK}    ; not filtered
         and TOGGLE      ; filter any other (logical) fall(en) edge
         and #{$FF ^ F_OPC ^ F_MNC}      ; auxiliaries should never TOGGLE
         sta TOGGLE
@@ -470,15 +510,16 @@ TMFFAL  ora #{F_NGN | F_BRK}    ; not filtered
         PAGE
 
 * move brake bit from ISTATE to STATES
-TMBRKMV bclr F_BRK_,STATES
-        brclr F_BRK_,ISTATE,TMEMGMV
+        bclr F_BRK_,STATES
+        brclr F_BRK_,ISTATE,TMF0BRK
         bset F_BRK_,STATES
+TMF0BRK equ *
 
 * toggle STATES F_EMG if TOGGLE F_EMG
-TMEMGMV brclr F_EMG_,TOGGLE,TMEMG0
+        brclr F_EMG_,TOGGLE,TMF0EMG
         lda STATES
         eor #F_EMG
-TMEMG0  sta STATES
+TMF0EMG sta STATES      ; STATES not yet valid!
 
 * turn on STATES turn signal if TOGGLE turn signal
 * (TOGGLE was filtered on trailing edge!)
@@ -489,47 +530,55 @@ TMEMG0  sta STATES
 * cancel STATES turn signal if TOGGLE F_CAN is not filtered out
         brclr F_CAN_,TOGGLE,TMCAN0
         and #{$FF ^ TURNSIG}    ; STATES still in A
-TMCAN0  sta STATES
+TMCAN0  sta STATES      ; STATES not yet valid!
+
+* if not timed out, STATES F_NGN should not yet be clear!
+        lda NGN_TIM+1
+        ora NGN_TIM
+        bne TMFNGN0
+        bset F_NGN_,STATES       ; might time out before RTI
+TMFNGN0 equ *
 
-*       Engine time out state is handled within the software timer
-* routines.
+* STATES is still not valid!
+* fall through to TMCLOCK
 
         SUBHEADER 'Timer Service Code -- Engine Time Out and Flasher Timers'
         PAGE
 
-*       Although the Real Time Interrupt is masked, the software clocks
-* use the RTI flag.  See RTIPOW for the RTI flag rate
-
 TMCLOCK
-        brclr RTIF_,TSCR,TIMDUN
-        bset RTIFR_,TSCR
-
-*       The engine time-out counter resets if NGN, EMG, or BRK toggles.
-* It runs only when the ISTATE F_NGN bit is low and the emergency
-* flashers and brakes (STATES F_EMG and F_BRK) are off.  It does not
-* underfow. The timer flags timeout in STATES F_NGN.
-
+* reset engine time-out if F_NGN, F_EMG, or F_BRK TOGGLEs
         lda TOGGLE
         and #{F_NGN | F_EMG | F_BRK}
-        beq TMNGN0      ; reset on toggle off (and on)
-        lda #{TIMOUT & $FF }            ; reset value low byte
+        beq TMORST
+        lda #{TIMOUT & $FF }    ; reset value low byte
         sta NGN_TIM+1
         lda #{TIMOUT / $100 + 1}        ; borrow on 0, not -1
         sta NGN_TIM
-        bra TMFLASH
+TMORST  equ *
+
+*       Although the Real Time Interrupt is masked, the software clocks
+* clock on the RTI flag.  See RTIPOW for the RTI flag rate
 
-TMNGN0
+        brclr RTIF_,TSCR,TIMDUN
+        bset RTIFR_,TSCR
+
+*       Engine time-out counter only runs when the ISTATE F_NGN bit is
+* low and the emergency flashers and brakes (STATES F_EMG and F_BRK) are
+* off.  Underflow is held off by cleared STATES F_NGN bit.  Communicates
+* with power down routine via STATES F_NGN.
+
+        brset F_NGN_,ISTATE,TMNGNR0
         lda STATES
         and #{F_NGN | F_EMG | F_BRK}    ; brakes or emg flashers?
-        eor #F_NGN                      ; engine already off?
-        bne TMFLASH
-        brset F_NGN_,ISTATE,TMFLASH     ; ISTATE F_NGN back on?
+        eor #F_NGN                      ; already counted out?
+        bne TMNGNR0
         dec NGN_TIM+1
-        bne TMFLASH      ; initial count is adjusted to make this work
+        bne TMNGNR0      ; initial count is adjusted to make this work
         dec NGN_TIM
-        bne TMFLASH
+        bne TMNGNR0
         bclr F_NGN_,STATES      ; signal timed out
         bset F_NGN_,TOGGLE      ; communicate change to STATES F_NGN
+TMNGNR0 equ *   ; Only now is STATES valid!
 
 *       The flasher counter runs only when STATES F_EMG, F_LFT, or F_RGT
 * are set.  When there are no flashers running, FLDARK is set, causing
@@ -542,19 +591,37 @@ TMFLASH lda #{F_EMG | TURNSIG}
         sta FLDARK
         lda #FLASH1
         sta FLASH
-        bra TIMDUN
+        bra TMNFLH
 
 TMFLH1  dec FLASH
-        bne TIMDUN
+        bne TMNFLH
         lda #FLASH1
-        com FDARK
+        com FLDARK
         bpl TMFLTM      ; result dark (1s) or light (0s)
         lda #FLASH0
 TMFLTM  sta FLASH
+TMNFLH  equ *
+
+*       It might be amusing to install a turn signal time out so that if
+* the turn signals remain flashing for more than ten minutes, they turn
+* themselves off.  The entire mechanism should fit here.  As mentioned
+* above, consider safety first!
 
 TIMDUN  rti
 $CYCLE_ADDER_OFF
 
+        swi     ; more unused ROM
+        swi
+        swi
+        swi
+        swi
+        swi
+        swi
+        swi
+        swi
+        swi
+        swi
+        swi
         swi
 
         SUBHEADER 'Initializations'
@@ -564,28 +631,28 @@ $CYCLE_ADDER_OFF
 * if SWI occurs, the machine is not in a defined state, and must reset
 IRQSRV
 SWISRV
-        clra
-        sta COPR
+        ldx #$5C        ; unique
+        stx COPR
         rsp     ; now falls through to RSTSRV
 
 * general inits
-RSTSRV  lda #ALLAMPS
+RSTSRV  lda #DRVLMPS
         sta PORTA       ; initial output values
-        lda #{ALLAMPS | DRVDRV}
+        lda #{DRVLMPS | DRVDRV}
         sta DDRA        ; set up directions
         sta PDRA        ; pull downs only on inputs
         clr PORTB       ; initial outputs (do port B just in case)
         clr DDRB        ; B initially input
         clr PDRB        ; with pull downs set
 * make sure EPROM programming stuff is out of the way
-        clr EPROG
+        clr EPROG       ; ICS05K complains, skip by hand
         clr PESCR
 * disable external interrupts
         bclr IRQE_,ISCR
         bset IRQR_,ISCR ; clear the flag
 * set up hardware timer
-        clra
-        sta COPR        ; b0 clear, about to change timer rate
+        ldx #$6A        ; unique use of X
+        stx COPR        ; b0 clear, about to change timer rate
         lda #{TOIE | RTIPOW}    ; only timer overflow interrupts
         sta TSCR                ; RTIPOW has the timer rate
         ora #{TOFR|RTIFR}       ; clear the flags
@@ -596,73 +663,130 @@ RSTSRV  lda #ALLAMPS
         sta DEBO+1      ; DEBO+2 is thrown out on first timer interrupt
         sta STATES      ; no unknown states
         sta ISTATE
-        sta TOGGLE      ; forces time-out counter to reset
+        lda #{TIMOUT & $FF }            ; reset time-out low byte
+        sta NGN_TIM+1
+        lda #{TIMOUT / $100 + 1}        ; counter borrows on 0, not -1
+        sta NGN_TIM
         lda #-1
         sta FLDARK      ; initial flash state is dark
         lda #FLASH1
         sta FLASH       ; initial flash time is on/light state
 
-
 * Falls through to DOSTATES
 
         SUBHEADER 'DOSTATES: Interpret States'
         PAGE
 
-DOSTATES:
-        wait
-        clra
-        sta COPR        ; tell COP we're in control
-
-* update the output state
-        lda #ALLAMPS    ; guess nothing shines
-STTBRK0 brclr F_EMG_,STATES,STTRGT      ; EMG has priority
-        and #{$FF ^ ALLAMPS}
+*       The debounce and timer routines make the output state machine
+* simple.  All indicator lamps are set according to the indicator STATES,
+* then masked by the current flasher output state (FLDARK).  Then, if the
+* brake light STATES bit is set, the rear lamps are forced on.  Then,
+* DRVDRV is only set if lamps are on (to save power when the engine is
+* off).
+
+*       Finally, if STATES F_NGN bit is clear, the power-down routine is
+* executed (and never returned from).  Again, requiring the time-out
+* counter to hold off the STATES engine-on bit may be a bit of a
+* semantic overload, but it seems more natural than making the STATES
+* F_NGN bit a mere mirror of ISTATE F_NGN, and then maintaining a
+* separate flag which would operate by the same rules as STATES F_NGN
+* does in the present design.  It also seems less data coupled than
+* having the power-down sense routine examine the internals of the
+* counter.
+
+*       FLDARK is used slightly ambiguously:  in the flasher timer
+* routine, bit 7 is used to determine whether to use the on period or
+* off period.  In the output state machine, below, all lamp bits are
+* used to mask out the signal lamps when the flasher says they should be
+* dark.  Rather than concern myself in several places with the state of
+* non-lamp bits, I mask them out where they could cause trouble.
 
-STTRGT  brclr F_LFT_,STATES,STTLFT
-        and #{$FF ^ LFTDRV}             ; assume never LFT & RGT both
-
-STTLFT  brclr F_RGT_,STATES,STTBRK      ; no flashers?
+DOSTATES:
+        wait    ; wait for something intelligible to debounce
+        ldx #$78        ; unique
+        stx COPR        ; tell COP we're in control
+
+* update the (inverted) lamp output state
+        lda #DRVLMPS    ; guess nothing shines (inverted drive)
+* A == lamp output state
+
+* now mask in inverted drive bits for any flashers that are on
+        brclr F_EMG_,STATES,STT0EMG
+        and #{$FF ^ DRVLMPS}
+STT0EMG equ *
+* A == lamp output state
+
+        brclr F_LFT_,STATES,STT0LFT
+        and #{$FF ^ LFTDRV}
+STT0LFT equ *
+* A == lamp output state
+
+        brclr F_RGT_,STATES,STT0RGT
         and #{$FF ^ RGTDRV}
+STT0RGT equ *
+* A == lamp output state
 
-STTFLH  ora FLDARK      ; mask out if flashers off
+* mask out flasher lamps if flasher is in off state
+        ora FLDARK
+* A == lamp output state
 
-STTBRK  brclr F_BRK_,STATES,STTLIT
-        and #{$FF ^ REARDRV}    ; brake has highest priority
-        and #ALLAMPS    ; filter out DRVDRV, in particular
+* check for brake lights
+STTBRK  brclr F_BRK_,STATES,STT0BRK
+        and #{$FF ^ REARDRV}    ; brake has higher priority than flash
+STT0BRK equ *
+* A == lamp output state
+
+        and #DRVLMPS    ; filter out extraneous bits
         sta FLMASK
-        lda STATES      ; do we need DRVDRV?
-        and #ANYLITE    ; avoid turning DRVDRV on and off:
-        beq STT0LIT
-        bset DRVDRV_    ; keep set during dark part of flash
+        eor #DRVLMPS    ; any lamps driven?
+        beq STT0FLH     ; invert the CCR zero bit and move it to DRVDRV
+        bset DRVDRV_,FLMASK
+STT0FLH equ *
+* now A is free
 
-STT0LIT lda PORTA
-        and #{$FF ^ ALLAMPS ^ DRVDRV}
+        lda PORTA
+        and #{$FF ^ DRVLMPS ^ DRVDRV}
         ora FLMASK
         sta PORTA
 
-        brclr F_NGN_,STATES,DOSTATES    ; all done until next time out
+* all done with lamps until next timer interrupt
+* loop to wait if engine not timed-out
+        brclr F_NGN_,STATES,DOSTATES
 
-* At this point, we know there has been neither engine nor flasher activity
-* for about five minutes.
+* At this point, we know there has been no engine, emergency flasher, or
+* brake activity for about five minutes.
 
 * go to power conserving state
-MNSTOP  lda #ALLAMPS    ; make sure they are off
-        sta PORTA       ; shut everything down, organized!
-        lda #{ALLAMPS | DRVDRV}
+* first shut down all lamps
+        lda #DRVLMPS    ; DRVDRV also off!
+* should be     lda #{DRVLMPS & ~DRVDRV} for maximum clarity
+        sta PORTA
+* now make sure power down state is valid!
+        lda #{DRVLMPS | DRVDRV}
         sta DDRA        ; set up directions
         sta PDRA        ; pull downs only on inputs
         clr PORTB       ; initial outputs (do port B just in case)
         clr DDRB        ; B initially input
         clr PDRB        ; with pull downs set
 * make sure EPROM programming stuff is out of the way
-        clr EPROG
+        clr EPROG       ; ICS complains, skip by hand
         clr PESCR
 * enable external interrupts
         bset IRQE_,ISCR ; DO NOT clear the flag (don't miss anything)
         stop    ; also shuts timer down
-        swi     ; should never come here (resets stack pointer)
-
+        swi     ; should never come here (IRQSRV resests stack pointer)
+        swi     ; more unused ROM
+        swi
+        swi
+        swi
+        swi
+        swi
+        swi
+        swi
+        swi
 
+*       Darn! I never found a way to use the personality EPROM bits for
+* a state machine!
 
 
         org VECTORS
@@ -672,3 +796,4 @@ MNSTOP  lda #ALLAMPS    ; make sure they are off
         fdb RSTSRV
 
         end
+