コミット: 770232dd4179d7fecd156d30e95eb3bab098b7ac - jmr6805break (git)

およそ20年前に、68HC05 の開発の練習に書いた車のブレイクライト・方向指示器コントローラです。

コミットメタ情報

• リビジョン: 770232dd4179d7fecd156d30e95eb3bab098b7ac (tree)
• 日時: 2013-07-08 21:35:39
• 作者: Joel Matthew Rees <reiisi@user...>
• コミッター: Joel Matthew Rees

ログメッセージ

Shift from asynchronous queued debounce to synchronous debounce, no queue.

変更サマリ

• delete: TURNSIGQ.AS2 => TURNSIG.AS3

差分

--- a/TURNSIGQ.AS2
+++ b/TURNSIG.AS3
@@ -15,7 +15,7 @@
 *       of
 *       South Salt Lake City
 *       Utah 
-*      
+*       
 
 
 
@@ -107,7 +107,7 @@
 *        |                    |
 *        +---5V_ZENER---GND   +---CENTER_BRK_LGHT---GND
 
-* PA2<---+---160K_OHM---ENG_ON_SW---12V
+* PA2<---+---160K_OHM---ENGINE_ON_SW---12V
 *        |
 *        +---5V_ZENER---GND
 
@@ -231,6 +231,13 @@
 * K-series MCUs, RESET should probably be tied high.  However, I suppose
 * it could make a good manual cancel-all input, if such is necessary.
 
+*       This assembler appears not to have a bit not function for
+* operand expressions.  So, I have in several places resorted to the
+* rather obtuse expedient of exclusive-orring bits to be reset with $FF,
+* ergo,                 AND #{$FF ^ F_OPC ^ F_MNC}
+* instead of            AND #~(F_OPC | F_MNC)
+* which I think is clearer.
+
         SUBHEADER 'Obligatory Mnemonics'
         PAGE
 $base   $0A
@@ -250,8 +257,8 @@ R_RDRV  equ B4
 R_RDRV_ equ B4_
 BRK_SW  equ B3
 BRK_SW_ equ B3_
-ENG_SW  equ B2
-ENG_SW_ equ B2_
+NGN_SW  equ B2          ; engine (ENG and EMG could be confusing)
+NGN_SW_ equ B2_
 DRVDRV  equ B1
 DRVDRV_ equ B1_
 CAN_BT  equ B0
@@ -265,7 +272,7 @@ RGT_BT_ equ B0_
 
 
 * logical input definitions for debounce and states
-* bits are remapped for debounce and queue speed
+* bits are remapped for debounce and speed
 * six bits of physical input, high two bits used for cancel logic
 F_LFT   equ LFT_BT
 F_LFT_  equ LFT_BT_
@@ -273,8 +280,8 @@ F_RGT   equ RGT_BT
 F_RGT_  equ RGT_BT_
 F_BRK   equ {BRK_SW < 2}        ; physical output bit
 F_BRK_  equ {BRK_SW_ + 2}
-F_ENG   equ {ENG_SW < 2}        ; physical output bit
-F_ENG_  equ {ENG_SW_ + 2}
+F_NGN   equ {NGN_SW < 2}        ; physical output bit
+F_NGN_  equ {NGN_SW_ + 2}
 F_EMG   equ {DRVDRV < 2}        ; fold onto output bit
 F_EMG_  equ {DRVDRV_ + 2}
 F_CAN   equ {CAN_BT < 2}
@@ -282,12 +289,6 @@ F_CAN_  equ {CAN_BT_ + 2}
 F_OPC   equ $40                 ; opposite direction cancel record
 F_MNC   equ $80                 ; manual cancel record
 
-*       Event queue constants
-* We only have 6 bit events and only record 4 in the queue.
-* Event scan algorithm wired to highest event bit in bit 3.
-
-MAXEVENTS       equ 6   ; more than max bit changes in "time slice"
-
         SUBHEADER 'Resource Definitions'
         PAGE
 
@@ -306,30 +307,24 @@ FLASH1  equ {32*XTAL/RTIRATE/2}         ; about 1/2 second
         org RAMBEG
 DEBO    rmb 3   ; the debounce record chain
 STABLE  rmb 1   ; temporary record of stable bits
-TOGGLQ  equ STABLE      ; temporary record of queue events
 TOGGLE  rmb 1   ; record of toggles
 ISTATE  rmb 1   ; record of the current input state
-QIN     rmb 1   ; queue input point
-QOUT    rmb 1   ; queue output point
-EVENTQ  rmb MAXEVENTS   ; no need to initialize this
 STATES  rmb 1   ; current controller states
-ENG_TIM rmb 2   ; engine time out timer
+NGN_TIM rmb 2   ; engine time out timer
 FLASH   rmb 1   ; flash timer
 FLTIME  rmb 1   ; flash flash time to load
-CANCEL  rmb 1   ; debounce for cancel button
-RETURN  rmb 1   ; debounce for return logic
 
 
 * ROM definitions follow:
         org ROMBEG
 
-        SUBHEADER 'Timer Service Code -- debounce'
+        SUBHEADER 'Timer Service Code'
         PAGE
 
-*       The timer service routine has five functions: debouncing the
-* inputs, directly setting the brake lights, loading the flasher event
-* queue, and maintaining two software clocks. Interrupts occur on timer
-* overflow (1024 CPU cycles).
+*       The timer service routine has these functions: debouncing the
+* inputs, directly setting the brake lights, flagging changes in TOGGLE,
+* adjusting STATES to match the inputs, and maintaining two software
+* clocks. Interrupts occur on timer overflow (1024 CPU cycles).
 
 *       The debounce routine translates the physical inputs to logical
 * inputs, maintains a record of the last three logical states sensed in
@@ -343,20 +338,36 @@ RETURN  rmb 1   ; debounce for return logic
 * happening to the inputs between timer overflows, and because there is
 * no mechanism for noise coincident and rythmic with timer overflow.
 
-*       The cancel TOGGLE bit is suppresed on same-direction rotation.
+*       The cancel TOGGLE bit is suppressed on same-direction rotation.
 * Trailing edge TOGGLEs are filtered out for all but brake and engine-on.
-* Cancel direction and manual cancel TOGGLEs are always filtered out.
+* Opposite direction cancel (F_OPC) and manual cancel (F_MNC) ISTATE
+* auxiliary flags are maintained to provide information on the source of
+* the F_CAN bit, and are always filtered out of TOGGLE.
+
+*       After adding an event queue and checking the timing results, two
+* things became clear: there is plenty of time to handle all the changes
+* to STATES without a queue, and TOGGLE makes a sort of horizontal queue
+* anyway.  In other words, there is no reason to make the adjustments to
+* STATES asynchronous when there is plenty of headroom for synchronous
+* adjustments.  Moreover, the adjustments take less time than organizing
+* the button events in a queue.  (Darn!  I was kind of proud of that six
+* byte queue, and the shift technique for storing events into it.)
+
+        SUBHEADER 'Timer Service Code -- Debounce and Toggle Filter'
+        PAGE
 
 $CYCLE_ADDER_ON
 TIMSRV  bset TOFR_,TSCR
-        lda DEBO+1      ; move the debounce chain
+
+* move the debounce chain
+        lda DEBO+1
         sta DEBO+2
         lda DEBO
         sta DEBO+1
 
-* read the inputs, converting physical to logical
+* read the static inputs, converting physical to logical
         lda PORTA
-        and #{BRK_SW | ENG_SW | CAN_BT }        ; clears F_EMG
+        and #{BRK_SW | NGN_SW | CAN_BT}         ; clears DRV_DRV
         bih TMMEMG      ; invert EMG and fold it in
         ora #F_EMG
 TMMEMG  lsra    ; remap
@@ -366,14 +377,15 @@ TMMEMG  lsra    ; remap
         ora DEBO
         sta DEBO
 
-* check for turn signal return and cancel
+* read the turn signal return and manual cancel auxiliary flags
+* (F_CAN & turn_sig_on) <=> read auxiliary flags
         bit #F_CAN      ; nothing at all without cancel
         beq TMSTGL
-        lda DDRB        ; meaningless when no turn signal
+        ldx DDRB        ; meaningless if not waiting for cancel
         beq TMSTGL
 $CYCLE_ADDER_OFF
 $CYCLE_ADDER_ON
-        tax
+        txa
         eor #{LFT_BT | RGT_BT}  ; strobe other side
         sta PORTB       ; set output state first
         sta DDRB        ; handy output state, huh?
@@ -390,9 +402,10 @@ TM0001  rora
 $CYCLE_ADDER_OFF
 $CYCLE_ADDER_ON
 
-* debounce inputs, set flags in TOGGLE
-TMSTGL  lda DEBO
-        eor DEBO+1
+* debounce inputs, set flags in TOGGLE and ISTATE
+* STABLE = ~((DEBO[0] ^ DEBO[1]) | (DEBO[1] ^ DEBO[2]))
+*
+TMSTGL  eor DEBO+1
         sta TOGGLE      ; re-use TOGGLE, TOGGLE not valid
         lda DEBO+1
         eor DEBO+2
@@ -404,7 +417,7 @@ TMSTGL  lda DEBO
         txa
         and ISTATE      ; look only at bits that are stable
         eor STABLE      ; flag bits that toggled
-        sta TOGGLE      ; TOGGLE valid, but not filtered
+        sta TOGGLE      ; true TOGGLEs, but not yet filtered
         coma            ; mask of non-toggles
         and ISTATE      ; old state of non-toggles
         sta ISTATE      ; (toggled bits cleared)
@@ -413,113 +426,80 @@ TMSTGL  lda DEBO
         ora ISTATE
         sta ISTATE      ; ISTATE now has current debounced inputs
 
-* filter TOGGLE F_CAN if same direction
+* filter out TOGGLE F_CAN if same direction
         bit #{F_OPC | F_MNC}    ; opposite direction or manual?
         bne TMFFAL
         bclr F_CAN_,TOGGLE      ; same direction
 
-* filter falling edge of F_LFT, F_RGT, F_EMG, F_CAN in TOGGLE
+* filter out trailing edge of F_LFT, F_RGT, F_EMG, F_CAN in TOGGLE
+* also filter out auxiliary TOGGLEs in passing
 * assumes ISTATE still in A
-TMFFAL  ora #{F_ENG | F_BRK}    ; not filtered
-        and TOGGLE      ; filter any other fall(en) edge
-        and #{$FF ^ F_OPC ^ F_MNC}      ; these should never TOGGLE
+TMFFAL  ora #{F_NGN | F_BRK}    ; not filtered
+        and TOGGLE      ; filter any other (logical) fall(en) edge
+        and #{$FF ^ F_OPC ^ F_MNC}      ; auxiliaries should never TOGGLE
         sta TOGGLE
 
-        SUBHEADER 'Timer Service Code -- brake lights'
+        SUBHEADER 'Timer Service Code -- Adjust STATES'
         PAGE
 
-*       Brake lights are the highest priority function, depending only
-* on the ISTATE F_BRK.  The STATES F_BRK is returned as a flag to other
-* routines.
-
-        brclr F_BRK_,ISTATE,TMBRK0
+* move brake bit from ISTATE to STATES
+TMBRKMV bclr F_BRK_,STATES
+        brclr F_BRK_,ISTATE,TMEMGMV
         bset F_BRK_,STATES
-        bclr R_LDRV_,PORTA      ; brake lights on
-        bclr R_RDRV_,PORTA
-* high center brake light connects directly to brake switch.
-        bra TMBRKDUN
-TMBRK0  bclr F_BRK_,STATES
-        bset R_LDRV_,PORTA      ; brake lights off
-        bset R_RDRV_,PORTA      ; (flashers can turn them back on)
-TMBRKDUN
-
-        SUBHEADER 'Timer Service Code -- fill event queue'
-        PAGE
 
-*       General debounce complete; now put signal events in queue:
-* Brake and engine-on are handled in TIMSRV, as synchronous events, and
-* so are not queued.  Turn signal and emergency inputs are positive edge
-* sensitive, falling edges are ignored.
+* toggle STATES F_EMG if TOGGLE F_EMG
+TMEMGMV brclr F_EMG_,TOGGLE,TMEMGM0
+        lda STATES
+        eor #F_EMG
+TMEMG0  sta STATES
 
-*       Queue is post-inc push and pull; QIN == QOUT is empty queue;
-* queue overflow causes the oldest event to be discarded, but should
-* never occur.
+* turn on STATES turn signal if TOGGLE turn signal
+        lda TOGGLE
+        and #{F_LFT | F_RGT}
+        ora STATES
 
-        lda TOGGLE      ; F_BRK & F_ENG are not queued!
-        and #{$FF ^ F_BRK ^ F_ENG}      ; KICS assembler has no bit not?
-        sta TOGGLQ
-        beq TMCLOCK     ; save time
-        ldx QIN
-        lda #$10        ; start with bit 3!
-*  cycles to this point, plus interrupt response (19 cycles)
+* cancel STATES turn signal if TOGGLE F_CAN is not filtered out
+        brclr F_CAN_,TOGGLE,TMCAN0
+        and #{$FF ^ F_LFT ^ F_RGT}      ; STATES still in A
+TMCAN0  sta STATES
 
-$CYCLE_ADDER_OFF
-$CYCLE_ADDER_ON
-TMQSCAN lsra            ; scan TOGGLE
-        beq TMQDUN
-        bit TOGGLQ
-        beq TMQSCAN
-* 12 cycles minimum time in loop
-$CYCLE_ADDER_OFF
-$CYCLE_ADDER_ON
-        sta ,x
-        incx
-        cpx #EVENTQ+MAXEVENTS
-        blo TMQNWRP
-        ldx #EVENTQ     ; 2 cycles
-TMQNWRP cpx QOUT
-        bne TMQSCAN
-        inc QOUT        ; 5 cycles
-TMQNBMP bra TMQSCAN     ; 3 cycles
-* 40 cycles maximum time in loop, (40 - 2 - 5 - 3) == 30 typical max;
-* Minimum queue time is 12 * 3 + 30 == 66 (no wrap, no bump);
-* max is 30 * 3 + 40 == 130 (one wrap, one bump max)
-$CYCLE_ADDER_OFF
-$CYCLE_ADDER_ON
-TMQDUN  stx QIN
+*       Engine time out state is handled within the software timer
+* routines.
 
-        SUBHEADER 'Timer Service Code -- engine time out and flasher timers'
+        SUBHEADER 'Timer Service Code -- Engine Time Out and Flasher Timers'
         PAGE
+
 *       Although the Real Time Interrupt is masked, the software clocks
-* use the RTI flag.  Selecting the fastest RTI rate gives the software
-* clocks a resolution of eight timer overflows (8192 CPU cycles).
+* use the RTI flag.  See RTIPOW for the RTI flag rate
 
 TMCLOCK
         brclr RTIF_,TSCR,TIMDUN
         bset RTIFR_,TSCR
 
-*       The engine time-out counter resets if the engine toggles on.  It
-* runs only when the ISTATE F_ENG bit is low and the emergency flashers
-* (STATES F_EMG) are off.  It does not underfow.  The timer flags
-* timeout in STATES F_ENG.
+*       The engine time-out counter resets if engine on toggles.  It
+* runs only when the ISTATE F_NGN bit is low and the emergency flashers
+* and brakes (STATES F_EMG and F_BRK) are off.  It does not underfow.
+* The timer flags timeout in STATES F_NGN.
 
-        brclr F_ENG_,TOGGLE,TMENG0
-        lda #{TIMOUT & $FF }    ; reset the clock
-        sta ENG_TIM+1
+        brclr F_NGN_,TOGGLE,TMNGN0      ; reset on toggle off (and on)
+        lda #{TIMOUT & $FF }            ; reset value low byte
+        sta NGN_TIM+1
         lda #{TIMOUT / $100 + 1}        ; borrow on 0, not -1
-        sta ENG_TIM                                  
+        sta NGN_TIM
         bra TMFLASH
 
-TMENG0
-        brset F_ENG_,ISTATE,TMFLASH
-        brset F_EMG_,STATES,TMFLASH
-        brclr F_ENG_,STATES,TMFLASH     ; do not underflow!
-        dec ENG_TIM+1
+TMNGN0
+        lda STATES
+        and #{F_NGN | F_EMG | F_BRK}    ; brakes or emg flashers?
+        eor #F_NGN                      ; no underflow
+        bne TMFLASH
+        brset F_NGN_,ISTATE,TMFLASH
+        dec NGN_TIM+1
         bne TIMFLH      ; initial count is adjusted to make this work
-        dec ENG_TIM
+        dec NGN_TIM
         bne TIMFLH
-        bclr F_ENG_,STATES      ; signal timed out
-        bset F_ENG_,TOGGLE      ; communicate with MAINLOOP
+        bclr F_NGN_,STATES      ; signal timed out
+        bset F_NGN_,TOGGLE      ; communicate with MAINLOOP
 
 * flasher counter
 TMFLASH lda #{F_EMG | F_LFT | F_RGT}
@@ -532,18 +512,18 @@ TMFLASH lda #{F_EMG | F_LFT | F_RGT}
 
 TIMDUN  rti
 $CYCLE_ADDER_OFF
-* Keep the maximum clock cycles in TIMSRV below half of TOFR period.
-* It is probably physically impossible to operate the switches fast
-* enough to overflow the queue that way.
 
         SUBHEADER 'Initializations'
         PAGE
+
 * waking up simply resets the MCU
 * if SWI occurs, the machine is not in a defined state, and must reset
 IRQSRV
-SWISRV  rsp     ; now falls through to RSTSRV
+SWISRV
         clra
         sta COPR
+        rsp     ; now falls through to RSTSRV
+
 * general inits
 RSTSRV  lda #{F_LDRV | F_RDRV | R_LDRV | R_RDRV}
         sta PORTA       ; initial output values
@@ -563,199 +543,93 @@ RSTSRV  lda #{F_LDRV | F_RDRV | R_LDRV | R_RDRV}
         clra
         sta COPR        ; b0 clear, about to change timer rate
         lda #{TOIE | RTIPOW}    ; only timer overflow interrupts
-        sta TSCR
+        sta TSCR                ; RTIPOW has the timer rate
         ora #{TOFR|RTIFR}       ; clear the flags
         sta TSCR
 * set up specific variables
         clr DEBO        ; start debounce chain clear
         clr DEBO+1      ; DEBO+2 is thrown out on first timer interrupt
-        lda #{F_ENG}
-        sta ISTATE      ; force TIMOUT to be set
-        sta TOGGLE
-        sta STATES      ; we think the engine is on
-        ldx #EVENTQ     ; empty QUEUE
-        stx QIN
-        stx QOUT
+        clr STATES      ; no unknown states
+        clr ISTATE
+* because F_NGN may not be on, and we don't depend on timer reset quirks:
+        lda #{TIMOUT & $FF }            ; reset value low byte
+        sta NGN_TIM+1
+        lda #{TIMOUT / $100 + 1}        ; borrow on 0, not -1
+        sta NGN_TIM
 
-* Falls through to MAINLOOP
+* Falls through to DOSTATES
 
-        SUBHEADER 'Dequeue Events and Modify STATES, also STOP'
+        SUBHEADER 'DOSTATES: Interpret States'
         PAGE
 
-MAINLOOP
+DOSTATES:
         cli     ; leave interrupts enabled as much as possible
         clra
         sta COPR        ; tell COP we're in control
-* check for STOP, dequeue flasher events, wait if necessary
-        sei
-        brclr F_ENG_,STATES,MNSTOP
-        ldx QOUT
-        cpx QIN ; QUEUE empty?
-        bne MNDEQUEUE
-        lda STATES              ; can we save power for a bit?
-        and #{F_LFT | F_RGT | F_BRK | F_EMG}
-        bne MNDRVWT
-        bclr DRVDRV_,PORTA
-MNDRVWT wait    ; enable interrupts, wait for timer
-        tst TOGGLE
-        beq MNDRVWT     ; nothing changed, nothing to respond to
-* with no activity, COP periodically resets the MCU system
-* this is not generally good engineering practice.
-        bset DRVDRV_,PORTA      ; IRQSRV might have driven the brake lights
-        bra MAINLOOP    ; check STOP and QUEUE again
-
-* go to power conserving state
-MNSTOP  lda #{F_LDRV | F_RDRV | R_LDRV | R_RDRV}
-        sta PORTA       ; shut everything down, organized!
-        lda #{F_LDRV | F_RDRV | R_LDRV | R_RDRV | DRVDRV}
-        sta DDRA        ; set up directions
-        sta PDRA        ; pull downs only on inputs
-        clr PORTB       ; initial outputs (do port B just in case)
-        clr DDRB        ; B initially input
-        clr PDRB        ; with pull downs set
-* make sure EPROM programming stuff is out of the way
-        clr EPROG
-        clr PESCR
-* enable external interrupts
-        bset IRQE_,ISCR ; DO NOT clear the flag (IRQ won't return)
-        stop    ; also shuts timer down
-        jmp SWISRV      ; should never come here (resets stack pointer)
-
-MNDEQUEUE
-        lda ,x
-        incx
-        cpx #EVENTQ+MAXEVENTS
-        blo MNQNWRP
-        ldx #EVENTQ
-MNQNWRP stx QOUT
-        cmp #F_EMG
-        bne MNCAN
-        eor STATES      ; toggle STATES F_EMG emergency flashers bit
-        sta STATES
-        bra MNDOSTATES
-
-MNQCAN  cmp #F_CAN
-        bne MNQLFT
-        ldx #7
-
-        lda STATES
-        and #{F_LFT | F_RGT}
-        beq MNDOSTATES
-        eor #{F_LFT | F_RGT}
-        sta TMPTURN
-        sta PORTB
-MNQCANL sta DDRB
-        brclr CAN_BT_,PORTA,MNQCANM     ; opposite direction?
-        incx
-MNQCANM clr DDRB        ; all outputs pulled down
-        brclr CAN_BT_,PORTA,MDQCANT     ; manual cancel?
-        incx
-        dec something
-        bne MNQCANL
-
-
-MNQLFT  cmp #F_LFT
-        bne MNQRGT
-        bset F_LFT_,STATES
-        bclr F_RGT_,STATES
-        bra MNDOSTATES
-
-MNQRGT  cmp #F_RGT
-        bne MNQDEF
-        bset F_RGT_,STATES
-        bclr F_LFT_,STATES
-        bra MNDOSTATES
-
-MNQDEF  jmp SWISRV      ; nothing else should be queued
-
-* then make the output mirror the state
-
-
-DOSTATE
-        brset F_BRK_,STATES,MAINLOOP    ; if brakes set, do nothing else
-        brset F_EMG_,STATES,DOEMERG     ; if emergency flash, skip engine
-        brset F_ENG_,STATES,DOTURN      ; no turn signals if engine off
-* engine off and timed out, no brakes, no emergency flashers
-        lda
-
-
-*       Emergency flasher filter simply toggles F_EMG bit of STATES
-* when emergency flasher button is pressed.  Release is ignored.
-
-INFEMG  cli     ; allow interrupts
-        sei     ; critical: not seamless access
-        brclr F_EMG_,TOGGLE,INFTRN
-        bclr F_EMG_,TOGGLE
-        brclr F_EMG_,ISTATE,INFTRN      ; no action when button released
-        lda STATES
-        eor #F_EMG
-        sta STATES
-* fall through
 
+* State machine for STATES
+* Brake, eNgine, emerGency, Left, and Right
 *
-
-INFTRN  cli     ; allow interrupts
-        sei     ; critical: not seamless access
-        lda STATES
-        and ISTATE
-        and #{F_LFT | F_RGT}    ; mask
-        eor #{F_LFT | F_RGT}    ; ignore if already on
-        and TOGGLE
-        beq FNENG
-        tax
-        and ISTATE      ; too late at night, all my work this aft is gone
-* check here for turning
-FNENG
-
-* support on and off states on signal timer.
-
-* if engine is off and timed out, shut down.
-* else if brakes on, set break lights, let front and turn signals flash
-* else if emergency set, flash all
-* else run turn signals
-
-
-* this should be discarded:
-
-* Four major state machines are implemented and maintained:
-*       ENGINE state, BRAKE state, EMERGENCY flasher state,
-*       and TURN_SIGNAL state.
-
-* If brake lights and emergency flashers are independent, EMERGENCY and
-* BRAKE states should be the only pieces of code that need modifying.
-
-
-* The ENGINE state machine has three states:
-*       ENG_OFF (MCU in STOP state)
-*       ENG_ON (MCU running, time out counter reset)
-*       ENG_TO (MCU running, time out counter counting)
-
-* The BRAKE state machine has two states:
-*       BRK_ON (F_BRK in ISTATE high, brake lights forced on)
-*       BRK_OFF (F_BRK in ISTATE low)
-
-* The EMERGENCY state machine has two states:
-*       EMG_ON (F_EMG in STATES high, flasher counters running)
-*       EMG_OFF (F_EMG in STATES low)
-* -- consider flasher rates, turnsignal vs emergency
-
-* The TURN_SIGNAL state machine has two state machines:
-
-*       BRK_OFF (F_BRK==1)---> BRK_ON   { possibly interrupting }
-*       BRK_OFF <---(F_BRK==0) BRK_ON
-
-*       ENG_OFF (F_ENG==1)---> ENG_ON   { usually interrupting }
-*               ENG_TMO <---(F_ENG==0) ENG_ON
-*               ENG_TMO (F_ENG==1)---> ENG_ON
-*       ENG_OFF <---(F_ENG==0 && 5 Minutes delay) ENG_TMO
-* (Change the XTAL constant if a 1 MHz crystal is not used!)
-
-*       EMG_NO (F_EMG==1 && EMG_FL==0)---> EMG_FL
+* B N G L R | output
+* ----------|------
+* 1 x x x x | Brake lights!
+* 0 x 1 x x | Emergency flashers!
+* 0 0 0 x x | Power Down
+* 0 1 0 0 0 | No outputs
+* 0 1 0 0 1 | Right turn signal
+* 0 1 0 1 0 | Left turn signal
+* 0 1 0 1 1 | NONE, clear turn signal states
 *
+* Cancel is entirely handled within TIMSRV
+
+        sei     ; is this necessary?
+        brset F_BRK_,STATES,STBRK
+        brset F_EMG_,STATES,STEMG
+        brclr F_EMG_,STATES,STNG0
+
+****** put turn signal code in here
+
+STBRK
+        bra DOSTATES
+
+STEMG
+        bra DOSTATES
+
+STNG0
+
+* had some power conserving in here
+*        lda STATES              ; can we save power for a bit?
+*        and #{F_LFT | F_RGT | F_BRK | F_EMG}
+*        bne MNDRVWT
+*        bclr DRVDRV_,PORTA
+*MNDRVWT wait    ; enable interrupts, wait for timer
+*        tst TOGGLE
+*        beq MNDRVWT     ; nothing changed, nothing to respond to
+** with no activity, COP periodically resets the MCU system
+** this is not generally good engineering practice.
+*        bset DRVDRV_,PORTA      ; IRQSRV might have driven the brake lights
+*        bra MAINLOOP    ; check STOP and QUEUE again
+*
+** go to power conserving state
+*MNSTOP  lda #{F_LDRV | F_RDRV | R_LDRV | R_RDRV}
+*        sta PORTA       ; shut everything down, organized!
+*        lda #{F_LDRV | F_RDRV | R_LDRV | R_RDRV | DRVDRV}
+*        sta DDRA        ; set up directions
+*        sta PDRA        ; pull downs only on inputs
+*        clr PORTB       ; initial outputs (do port B just in case)
+*        clr DDRB        ; B initially input
+*        clr PDRB        ; with pull downs set
+** make sure EPROM programming stuff is out of the way
+*        clr EPROG
+*        clr PESCR
+** enable external interrupts
+*        bset IRQE_,ISCR ; DO NOT clear the flag (IRQ won't return)
+*        stop    ; also shuts timer down
+*        jmp SWISRV      ; should never come here (resets stack pointer)
+
+        bra DOSTATES
 
 
-        bra MAINLOOP
-
 
         org VECTORS
         fdb TIMSRV