コミット: 4ab5c3b066d5a8b0c0f5be069e9225e4601e9435 - jmr6805break (git)

およそ20年前に、68HC05 の開発の練習に書いた車のブレイクライト・方向指示器コントローラです。

コミットメタ情報

• リビジョン: 4ab5c3b066d5a8b0c0f5be069e9225e4601e9435 (tree)
• 日時: 2013-07-08 20:10:59
• 作者: Joel Matthew Rees <reiisi@user...>
• コミッター: Joel Matthew Rees

ログメッセージ

Second backup. Nothing stands out besides work on debouncing and decoding.

変更サマリ

• delete: TURNSIG.AS0 => TURNSIG.AS1

差分

--- a/TURNSIG.AS0
+++ b/TURNSIG.AS1
@@ -2,15 +2,20 @@
         HEADER 'Turn Signal Switch by Joel Matthew Rees'
 
 * Electronic Turn Signal and Emergency Flasher Switch/Timer
+*       Version 1.00
 *       Implemented on the 68HC(7)05Kx
 *       Assembled and tested on the M68HC705KICS
+*
 *       Copyright 1993 Joel Matthew Rees
+*
+*       Permission granted in advance for strictly non-profit
+* educational use.  All other rights retained by the author.
 
 * Authored by Joel Matthew Rees, June to August 1993
 *       of
 *       South Salt Lake City
 *       Utah 
-*       
+*      
 
 
 
@@ -35,7 +40,8 @@
 * switch back to mind.  I thought ten bits of I/O, internal timers,
 * and the STOP mode would be sufficient to replicate the logic of that
 * switch assembly, adding directional turn signal return switches and
-* flasher logic as well.  It turned out to be a tight squeeze.
+* flasher and turn sgnal return logic as well.  It turned out to be a
+* tight squeeze.
 
 *       The intent of this document is to focus on the problems of
 * decoding inputs, directionalizing the turn signal return, eliminating
@@ -44,7 +50,8 @@
 * electro-static discharge protection (very important in automotive
 * applications), and details of lamp driver circuits are mostly set
 * aside.  The logic has been tested with the M68HC705KICS simulator
-* program, but has not been tested in physical mock up or real vehicle.
+* program, but has not been tested in a physical mock up or real
+* vehicle.
 
 *       One of the objects of this design was to replace mechanical
 * parts (that tend to flow in hot climates and become brittle in cold)
@@ -66,15 +73,16 @@
 *       The turn signal return mechanism is a pair of reed relays
 * mounted inside the bottom of the steering column cowling about ten
 * degrees apart, with three magnetic actuators mounted to the steering
-* shaft at ten o'clock, two o'clock, and six o'clock.  (Four magnets in
-* an x pattern might also be workable, I haven't reworked the angular
-* timing to be sure.)  The shape and position of the magnets and reeds
-* should be such that the reeds close only once as a magnet passes, and
-* such that the reeds have about ten degrees of overlapping actuation.
-* The overlap in actuation helps determine the direction the steering
-* wheel is rotating.  Minor changes to the software should allow the use
-* of optical sensors, but I have the impression the magnetic devices are
-* more immune to extremes of climate.
+* shaft at ten o'clock, two o'clock, and six o'clock.  (More magnets and
+* other patterns might also be workable, but they should be tested in
+* real steering assembly before the design is locked in.  The shape and
+* position of the magnets and reeds should be such that the reeds close
+* only once as a magnet passes, and such that the reeds have about ten
+* degrees of overlapping actuation. The overlap in actuation helps
+* determine the direction the steering wheel is rotating.  Minor changes
+* to the design should allow the use of optical sensors, but I have the
+* impression that magnetic devices are more immune to extremes of
+* climate.
 
         SUBHEADER 'Model Schematic'
         PAGE
@@ -106,11 +114,11 @@
 *        +---5V_ZENER---GND
 
 * PA1>---DRVRS_ON_CNTRL
-*
+
 * IRQ<---+---100K_OHM---Vdd
 *        |
 *        +---EMG_SW---GND
-*
+
 * PB1<>--+----------LEFT_RETURN_SW---+
 *        |                           |
 *        +---LEFT_TURN_SW---+        |
@@ -140,9 +148,8 @@
 * active high.
 
 *       I arbitrarily assume the signal lamp drivers will be active low.
-* Who could say why?  I considered attempting to hide this assumption in
-* a macro but I'll skip that complexity.  It shouldn't be too hard to
-* find all the places to invert the outputs.
+* Who could say why?  However, I have hidden this assumption in a macro
+* so I don't have to remember it.
 
 *       Hanging the indicators and the audio feedback on the front lamp
 * drivers separates them from brake activity.  Two audio feedback
@@ -167,27 +174,34 @@
 * natural match for IRQ.
 
 *       The right turn signal return switch is positioned about five
-* degrees right of bottom, and the left return is positioned the same
-* distance to the left.  In this way, when the steering wheel rotates,
-* the return switch for the direction of rotation actuates first, then
-* the opposite direction switch closes, then the same direction switch
-* opens, and then the opposite direction switch opens.  Thus, when
-* restoring from a turn, the return switch for the appropriate direction
-* closes after the other switch.  In other words, if you turn right, the
-* steering wheel will be rotate to the left when you restore to the
-* straight, and the switches actuate from left to right during the
-* restore.
+* degrees right of bottom of the steering column housing, and the left
+* return is positioned the same distance to the left.  In this way, when
+* the steering wheel rotates, the return switch for the direction of
+* rotation actuates first, then the opposite direction switch closes,
+* then the same direction switch opens, and then the opposite direction
+* switch opens.  Thus, when restoring from a turn, the return switch for
+* the appropriate direction closes after the other switch.  In other
+* words, if you turn right, the steering wheel will be rotate to the
+* left when you return to straight, and the switches actuate from left
+* to right during the restore.
 
 *       When both turn signals are off, both turn signal ports are set
 * as inputs.  When a turn signal switch input senses a closure, that
 * port is made an output and driven high.  When the cancel input senses
-* a closure, the turn signal ports are restored to both input.  If the
-* cancel input remains high, a manual cancel is decoded.  If not, the
-* other direction input is made output and driven high.  If the cancel
-* input remains high now, the other direction switch closed first, and a
-* restoring rotation is decoded.  If not, same direction rotation is
-* decoded, so the opposite direction port is returned to input, and the
-* original direction port is again made output and driven high.
+* a closure, the turn signal ports are restored to both input.
+
+*       If the cancel input remains high, a manual cancel is decoded.
+* If not, the other direction input is made output and driven high.  If
+* the cancel input returns high now, the other direction switch closed
+* first, and a restoring rotation is decoded.  If not, same direction
+* rotation is decoded; then the the opposite direction port is returned
+* to input, and the original direction port is again made output and
+* driven high to wait again.
+
+*       In the meantime, if the opposite direction turn signal input
+* senses a closure, then it is assumed that the operator changed his
+* mind without hitting the manual cancel, and the roles of the turn
+* signal I/O bits are reversed.
 
 *       A peculiar characteristic of this design is the apparent lack of
 * use for the RESET input.  Since power-on reset is built in to the
@@ -196,6 +210,7 @@
 
         SUBHEADER 'Obligatory Mnemonics'
         PAGE
+$base   $0A
 $include "68HC05K.EQU"
 
         SUBHEADER 'Program Mnemonics'
@@ -227,38 +242,54 @@ RGT_BT_ equ B0_
 
 
 * logical input definitions for debounce and states
-F_LFT   equ {LFT_BT < 4}        ; fold onto output
-F_LFT_  equ {LFT_BT + 4}
-F_RGT   equ {RGT_BT < 4}        ; fold onto output
-F_RGT_  equ {RGT_BT + 4}
-F_BRK   equ BRK_SW
-F_BRK_  equ BRK_SW_
-F_ENG   equ ENG_SW
-F_ENG_  equ ENG_SW_
-F_EMG   equ DRVDRV      ; fold onto output
-F_EMG_  equ DRVDRV_
-F_CAN   equ CAN_BT
-F_CAN_  equ CAN_BT_
-
+* bits are remapped for debounce and queue speed
+F_LFT   equ LFT_BT
+F_LFT_  equ LFT_BT_
+F_RGT   equ RGT_BT
+F_RGT_  equ RGT_BT_
+F_BRK   equ {BRK_SW < 2}        ; physical output bit
+F_BRK_  equ {BRK_SW_ + 2}
+F_ENG   equ {ENG_SW < 2}        ; physical output bit
+F_ENG_  equ {ENG_SW_ + 2}
+F_EMG   equ {DRVDRV < 2}        ; fold onto output bit
+F_EMG_  equ {DRVDRV_ + 2}
+F_CAN   equ {CAN_BT < 2}
+F_CAN_  equ {CAN_BT_ + 2}
+
+*       Event queue constants
+* We only have 6 bit events and only record 4 in the queue.
+* Event scan algorithm wired to highest event bit in bit 3.
+
+MAXEVENTS       equ 6   ; more than max bit changes in "time slice"
 
         SUBHEADER 'Resource Definitions'
         PAGE
 
 * crystal frequency, in MHz:
 XTAL    equ 1
+RTIPOW  equ 1   ; ls bits is right place for timer hardware
+RTIRATE equ {2 < RTIPOW}        ; 2 ^ RTIPOW stored is actual divide
+TIMOUT  equ {9155*XTAL/RTIRATE+1}       ; 5 minutes (if XTAL equ is correct)
+* only one flash rate, 2/3 duty cycle
+FLASH0  equ {32*XTAL/RTIRATE/4}         ; about 1/4 second
+FLASH1  equ {32*XTAL/RTIRATE/2}         ; about 1/2 second
 
         org MOR
         fcb {PIN3 | RC | PIRQ | COPEN}
 
-
         org RAMBEG
 DEBO    rmb 3   ; the debounce record chain
+STABLE  rmb 1   ; temporary record of stable bits
+TOGGLQ  equ STABLE      ; temporary record of queue events
 TOGGLE  rmb 1   ; record of toggles
-STABLE  rmb 1   ; timer service temporary
 ISTATE  rmb 1   ; record of the current input state
+QIN     rmb 1   ; queue input point
+QOUT    rmb 1   ; queue output point
+EVENTQ  rmb MAXEVENTS   ; no need to initialize this
 STATES  rmb 1   ; current controller states
 ENG_TIM rmb 2   ; engine time out timer
-SOFTIM  rmb 2   ; flash timer
+FLASH   rmb 1   ; flash timer
+FLTIME  rmb 1   ; flash flash time to load
 
 
 * ROM definitions follow:
@@ -266,22 +297,21 @@ SOFTIM  rmb 2   ; flash timer
 
         SUBHEADER 'Timer Service Code -- debounce'
         PAGE
-*       The timer service routine has two functions: debouncing the
-* inputs and maintaining the software clocks.  Interrupts occur on timer
+*       The timer service routine has five functions: debouncing the
+* inputs, directly setting the brake lights, loading the flasher event
+* queue, and maintaining two software clocks. Interrupts occur on timer
 * overflow (1024 CPU cycles).
 
 *       The debounce routine translates the physical inputs to logical
 * inputs, maintains a record of the last three logical states sensed in
 * DEBO, debounces each input on three identical states, flags changes in
 * the debounced input in TOGGLE, and leaves the current debounced input
-* in ISTATE.  STABLE is a local variable with dynamic scope.
-
-*       Since debouncing occurs on three identical states, the debounce
-* period is between two and three timer overflows -- 4 to 6 mS with a
-* 1 MHz crystal, 2 to 3 mS with a 2 MHz crystal.
-
-*       Debouncing ignores the return switch logic.
+* in ISTATE.  Since debouncing occurs on three identical states, the
+* debounce period is between two and three timer overflows -- 4 to 6 mS
+* with a 1 MHz crystal, 2 to 3 mS with a 2 MHz crystal.  Debouncing
+* ignores the return switch logic and related activities.
 
+$CYCLE_ADDER_ON
 TIMSRV  bset TOFR_,TSCR
         lda DEBO+1      ; move the debounce chain
         sta DEBO+2
@@ -289,67 +319,147 @@ TIMSRV  bset TOFR_,TSCR
         sta DEBO+1
 * read the inputs, converting physical to logical
         lda PORTB       ; PB2-7 always read 0
-        lsla            ; move bits to flag positions
-        lsla
-        lsla
-        lsla
-        sta DEBO        ; B read complete
+        sta DEBO
         lda PORTA
         and #{BRK_SW | ENG_SW | CAN_BT }        ; clears F_EMG
         bih TIM0MG      ; invert EMG and fold it in
         ora #F_EMG
-TIM0MG  ora DEBO
+TIM0MG  lsra    ; remap
+        lsra
+        ora DEBO
         sta DEBO        ; current state
-
 * debounce inputs, set flags in TOGGLE
         lda DEBO
         eor DEBO+1
-        sta TOGGLE      ; re-use! (TOGGLE not valid)
+        sta TOGGLE      ; re-use TOGGLE, TOGGLE not valid
         lda DEBO+1
         eor DEBO+2
         ora TOGGLE      ; a bit for any input that bounced
-        coma            ; bits that did not bounce are set
+        coma            ; bits that bounced are clear
         tax
         and DEBO+2      ; state of stable bits
-        sta STABLE      ; (unstable bits cleared)
+        sta STABLE      ; (unstable bits still clear)
         txa
-        and ISTATE      ; clear bits that are now unstable
+        and ISTATE      ; look only at bits that are stable
         eor STABLE      ; flag bits that toggled
         sta TOGGLE      ; TOGGLE now valid
         coma            ; mask of non-toggles
         and ISTATE      ; old state of non-toggles
         sta ISTATE      ; (toggled bits cleared)
         lda TOGGLE      ; mask of toggles
-        and DEBO+2      ; new states
+        and STABLE      ; new states of bits that toggled
         ora ISTATE
         sta ISTATE      ; ISTATE now has current debounced inputs
 
-        SUBHEADER 'Timer Service Code -- timers'
+        SUBHEADER 'Timer Service Code -- brake lights'
+        PAGE
+*       Brake lights are the highest priority function, depending only
+* on the ISTATE F_BRK.  The STATES F_BRK is returned as a flag to other
+* routines.
+
+        brclr F_BRK_,ISTATE,TMBRK0
+        bset F_BRK_,STATES
+        bclr R_LDRV_,PORTA      ; brake lights on
+        bclr R_RDRV_,PORTA
+* high center brake light connects directly to brake switch.
+        bra TMBRKDUN
+TMBRK0  bclr F_BRK_,STATES
+        bset R_LDRV_,PORTA      ; brake lights off
+        bset R_RDRV_,PORTA      ; (flashers can turn them back on)
+TMBRKDUN
+
+        SUBHEADER 'Timer Service Code -- fill event queue'
+        PAGE
+*       General debounce complete; now put signal events in queue:
+* Brake and engine-on are handled in TIMSRV, as synchronous events, and
+* so are not queued.  Turn signal and emergency inputs are positive edge
+* sensitive, falling edges are ignored.
+
+*       Queue is post-inc push and pull; QIN == QOUT is empty queue;
+* queue overflow causes the oldest event to be discarded, but should
+* never occur.
+
+        lda TOGGLE      ; F_BRK & F_ENG are not queued!
+        and #{$FF ^ F_BRK ^ F_ENG}      ; KICS assembler has no bit not?
+        and ISTATE      ; queue only TOGGLE on
+        sta TOGGLQ
+        beq TMCLOCK     ; save time
+        ldx QIN
+        lda #$10        ; start with bit 3!
+*  cycles to this point, plus interrupt response (19 cycles)
+
+$CYCLE_ADDER_OFF
+$CYCLE_ADDER_ON
+TMQSCAN lsra            ; scan TOGGLE
+        beq TMQDUN
+        bit TOGGLQ
+        beq TMQSCAN
+* 12 cycles minimum time in loop
+$CYCLE_ADDER_OFF
+$CYCLE_ADDER_ON
+        sta ,x
+        incx
+        cpx #EVENTQ+MAXEVENTS
+        blo TMQNWRP
+        ldx #EVENTQ     ; 2 cycles
+TMQNWRP cpx QOUT
+        bne TMQSCAN
+        inc QOUT        ; 5 cycles
+TMQNBMP bra TMQSCAN     ; 3 cycles
+* 40 cycles maximum time in loop, (40 - 2 - 5 - 3) == 30 typical max;
+* Minimum queue time is 12 * 3 + 30 == 66 (no wrap, no bump);
+* max is 30 * 3 + 40 == 130 (one wrap, one bump max)
+$CYCLE_ADDER_OFF
+$CYCLE_ADDER_ON
+TMQDUN  stx QIN
+
+        SUBHEADER 'Timer Service Code -- engine time out and flasher timers'
         PAGE
 *       Although the Real Time Interrupt is masked, the software clocks
 * use the RTI flag.  Selecting the fastest RTI rate gives the software
 * clocks a resolution of eight timer overflows (8192 CPU cycles).
 
-*       The engine timeout counter is not allowed to underflow
-
-* time to clock?
+TMCLOCK
         brclr RTIF_,TSCR,TIMDUN
         bset RTIFR_,TSCR
-* engine time out counter:
-        brset F_ENG_,ISTATE,TIMFLH      ; avoid wasting time here
+
+*       The engine time-out counter resets if the engine toggles on.  It
+* runs only when the ISTATE F_ENG bit is low and the emergency flashers
+* (STATES F_EMG) are off.  It does not underfow.  The timer flags
+* timeout in STATES F_ENG.
+
+        brclr F_ENG_,TOGGLE,TMENG0
+        lda #{TIMOUT & $FF }    ; reset the clock
+        sta ENG_TIM+1
+        lda #{TIMOUT / $100 + 1}        ; borrow on 0, not -1
+        sta ENG_TIM                                  
+        bra TMFLASH
+
+TMENG0
+        brset F_ENG_,ISTATE,TMFLASH
+        brset F_EMG_,STATES,TMFLASH
+        brclr F_ENG_,STATES,TMFLASH     ; do not underflow!
         dec ENG_TIM+1
         bne TIMFLH      ; initial count is adjusted to make this work
         dec ENG_TIM
         bne TIMFLH
-        clr ENG_TIM+1   ; no underflow
-        clr ENG_TIM
-        bset F_ENG_,STATES      ; signal timed out
-TIMFLH
-        inc SOFTIM+1
+        bclr F_ENG_,STATES      ; signal timed out
+        bset F_ENG_,TOGGLE      ; communicate with MAINLOOP
+
+* flasher counter
+TMFLASH lda #{F_EMG | F_LFT | F_RGT}
+        and STATES      ; flasher active?
+        beq TIMDUN
+        dec FLASH
         bne TIMDUN
-        inc SOFTIM
-TIMDUN  rti     ; careful with the interrupt service time!
+        lda FLTIME
+        sta FLASH
 
+TIMDUN  rti
+$CYCLE_ADDER_OFF
+* Keep the maximum clock cycles in TIMSRV below half of TOFR period.
+* It is probably physically impossible to operate the switches fast
+* enough to overflow the queue that way.
 
         SUBHEADER 'Initializations'
         PAGE
@@ -357,9 +467,10 @@ TIMDUN  rti     ; careful with the interrupt service time!
 * if SWI occurs, the machine is not in a defined state, and must reset
 IRQSRV
 SWISRV  rsp     ; now falls through to RSTSRV
+        clra
+        sta COPR
 * general inits
-RSTSRV  clr COPR        ; just in case
-        lda #{F_LDRV | F_RDRV | R_LDRV | R_RDRV}
+RSTSRV  lda #{F_LDRV | F_RDRV | R_LDRV | R_RDRV}
         sta PORTA       ; initial output values
         lda #{F_LDRV | F_RDRV | R_LDRV | R_RDRV | DRVDRV}
         sta DDRA        ; set up directions
@@ -373,67 +484,166 @@ RSTSRV  clr COPR        ; just in case
 * disable external interrupts
         bclr IRQE_,ISCR
         bset IRQR_,ISCR ; clear the flag
-* clear RAM
-        ldx #RAMBEG
-        lda #RAMSIZ
-RSTCLR  clr ,x          ; this is probably a waste?
-        incx
-        deca
-        bne RSTCLR
 * set up hardware timer
-        clr COPR        ; the manual suggests doing this before timer rate
-        lda #TOIE       ; only timer overflow interrupts
-        sta TSCR        ; and the fastest Real Time rate
+        clra
+        sta COPR        ; b0 clear, about to change timer rate
+        lda #{TOIE | RTIPOW}    ; only timer overflow interrupts
+        sta TSCR
         ora #{TOFR|RTIFR}       ; clear the flags
         sta TSCR
 * set up specific variables
+        clr DEBO        ; start debounce chain clear
+        clr DEBO+1      ; DEBO+2 is thrown out on first timer interrupt
         lda #{F_ENG}
-        sta ISTATE      ; we know the engine is on!
+        sta ISTATE      ; force TIMOUT to be set
         sta TOGGLE
-        sta STATES
+        sta STATES      ; we think the engine is on
+        ldx #EVENTQ     ; empty QUEUE
+        stx QIN
+        stx QOUT
 
-MAINLOOP
-* Assume interrupts enabled, except for brief critical sections
-* Falls through to input filter functions
+* Falls through to MAINLOOP
 
-        SUBHEADER 'Main function: input filter state machines'
+        SUBHEADER 'STOP and dequeue'
         PAGE
 
-*       Engine on filter resets the toggle bit and sets the timer if
-* toggled off.  STATES bit is handled by TIMSRV.
+MAINLOOP
+        cli     ; leave interrupts enabled as much as possible
+        clra
+        sta COPR        ; tell COP we're in control
+* check for STOP, dequeue flasher events, wait if necessary
+        sei
+        brclr F_ENG_,STATES,MNSTOP
+        ldx QOUT
+        cpx QIN ; QUEUE empty?
+        bne MNDEQUEUE
+        lda STATES              ; can we save power for a bit?
+        and #{F_LFT | F_RGT | F_BRK | F_EMG}
+        bne MNDRVWT
+        bclr DRVDRV_,PORTA
+MNDRVWT wait    ; enable interrupts, wait for timer
+        tst TOGGLE
+        beq MNDRVWT     ; nothing changed, nothing to respond to
+* with no activity, COP periodically resets the MCU system
+* this is not generally good engineering practice.
+        bset DRVDRV_,PORTA      ; IRQSRV might have driven the brake lights
+        bra MAINLOOP    ; check STOP and QUEUE again
+
+* go to power conserving state
+MNSTOP  lda #{F_LDRV | F_RDRV | R_LDRV | R_RDRV}
+        sta PORTA       ; shut everything down, organized!
+        lda #{F_LDRV | F_RDRV | R_LDRV | R_RDRV | DRVDRV}
+        sta DDRA        ; set up directions
+        sta PDRA        ; pull downs only on inputs
+        clr PORTB       ; initial outputs (do port B just in case)
+        clr DDRB        ; B initially input
+        clr PDRB        ; with pull downs set
+* make sure EPROM programming stuff is out of the way
+        clr EPROG
+        clr PESCR
+* enable external interrupts
+        bset IRQE_,ISCR ; DO NOT clear the flag (IRQ won't return)
+        stop    ; also shuts timer down
+        jmp SWISRV      ; should never come here (resets stack pointer)
 
-TIMOUT  EQU 18311/XTAL          ; 5 minutes (if XTAL equ is correct)
+MNDEQUEUE
+        lda ,x
+        incx
+        cpx #EVENTQ+MAXEVENTS
+        blo MNQNWRP
+        ldx #EVENTQ
+MNQNWRP stx QOUT
+        cmp #F_EMG
+        bne MNCAN
+        eor STATES      ; toggle STATES F_EMG emergency flashers bit
+        sta STATES
+        bra MNDOSTATES
+
+MNQCAN  cmp #F_CAN
+        bne MNQLFT
+        lda DDRB
+        eor #3
+
+        clr DDRB
+        bsr CANDEBO
+        cmp #6
+        blo MNQCAND
+        bset F_CAN_,STATES
+        bra MNDOSTATES
+MNQCAND lda STATES
+        and #{F_LFT | F_RGT}
+        eor #{F_LFT | F_RGT}    ; other port
+        sta DDRB
+        bsr CANDEBO
+
+
+MNQLFT  cmp #F_LFT
+        bne MNQRGT
+        bset F_LFT_,STATES
+        bclr F_RGT_,STATES
+        bra MNDOSTATES
+
+MNQRGT  cmp #F_RGT
+        bne MNQDEF
+        bset F_RGT_,STATES
+        bclr F_LFT_,STATES
+        bra MNDOSTATES
+
+MNQDEF  jmp SWISRV      ; nothing else should be queued
+
+* subroutine to quickly "debounce" the cancel input
+* reads CAN_BT eight times, summing the bits into A
+* trashes X
+$CYCLE_ADDER_ON
+CANDEBO ldx #8
+        clra
+        brclr CAN_BT_,PORTA,CANDEB1     ; get CAN_BT into carry
+CANDEB1 adc #0
+        decx
+        bne CANDEBO
+$CYCLE_ADDER_OFF
+* about 1/4 mS at 1 MHz, sufficient to believe the input bit
+        rts
+
+
+* then make the output mirror the state
+
+
+DOSTATE
+        brset F_BRK_,STATES,MAINLOOP    ; if brakes set, do nothing else
+        brset F_EMG_,STATES,DOEMERG     ; if emergency flash, skip engine
+        brset F_ENG_,STATES,DOTURN      ; no turn signals if engine off
+* engine off and timed out, no brakes, no emergency flashers
+        lda
 
-INFENG  cli     ; allow interrupts
-        sei     ; critical: not seamless access
-        brclr F_ENG_,TOGGLE,INFEMG
-        bclr F_ENG_,TOGGLE
-        brset F_ENG_,ISTATE,INFEMG      ; engine on input toggled off
-        lda #{TIMOUT & $FF}
-        sta ENG_TIM+1
-        lda #{TIMOUT / 256 + 1}         ; counter borrows on 0, not -1
-        sta ENG_TIM
-* fall through
 
 *       Emergency flasher filter simply toggles F_EMG bit of STATES
-* when emergency flasher button is pressed.
+* when emergency flasher button is pressed.  Release is ignored.
 
 INFEMG  cli     ; allow interrupts
         sei     ; critical: not seamless access
         brclr F_EMG_,TOGGLE,INFTRN
         bclr F_EMG_,TOGGLE
         brclr F_EMG_,ISTATE,INFTRN      ; no action when button released
-        lda #F_EMG
-        eor STATES
+        lda STATES
+        eor #F_EMG
         sta STATES
 * fall through
 
 *
+
 INFTRN  cli     ; allow interrupts
         sei     ; critical: not seamless access
-
-
-* stuff in state machines:
+        lda STATES
+        and ISTATE
+        and #{F_LFT | F_RGT}    ; mask
+        eor #{F_LFT | F_RGT}    ; ignore if already on
+        and TOGGLE
+        beq FNENG
+        tax
+        and ISTATE      ; too late at night, all my work this aft is gone
+* check here for turning
+FNENG
 
 * support on and off states on signal timer.
 
@@ -481,12 +691,8 @@ INFTRN  cli     ; allow interrupts
 *       EMG_NO (F_EMG==1 && EMG_FL==0)---> EMG_FL
 *
 
-        wait
-        clr COPR
-        tst TOGGLE
-        beq FUNSTATE
 
-        bra WAITLOOP
+        bra MAINLOOP
 
 
         org VECTORS