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GNU Binutils with patches for OS216


コミットメタ情報

リビジョンbe6a24d8eabdbeef32a9d79e81307af4491fcf56 (tree)
日時2017-04-26 00:07:00
作者Claudiu Zissulescu <claziss@syno...>
コミッターclaziss

ログメッセージ

[ARC] Prefer NOP instead of MOV 0,0

NOP and MOV 0,0 are having the same encoding. As MOV mnemonic is
located before NOP in the instruction table, the disassembler prints
MOV 0,0 for NOP. Reorder the instructions such that NOP is first.

gas/
2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>

* testsuite/gas/arc/b.d: Update test.
* testsuite/gas/arc/noargs_hs.d: Likewise.

opcode/
2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>

* arc-tbl.h: Reorder NOP entry to be before MOV instructions.

変更サマリ

差分

--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
1+2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
2+
3+ * testsuite/gas/arc/b.d: Update test.
4+ * testsuite/gas/arc/noargs_hs.d: Likewise.
5+
16 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
27
38 * config/tc-mips.c (md_convert_frag): Correct
--- a/gas/testsuite/gas/arc/b.d
+++ b/gas/testsuite/gas/arc/b.d
@@ -35,12 +35,12 @@ Disassembly of section .text:
3535 68: 0798 ffce bls -104
3636 6c: 0794 ffcf bpnz -108
3737 70: 0791 ffef b.d 0 <text_label>
38- 74: 264a 7000 mov 0,0
38+ 74: 264a 7000 nop
3939 78: 0789 ffcf b 0 <text_label>
4040 7c: 0785 ffef b.d 0 <text_label>
41- 80: 264a 7000 mov 0,0
41+ 80: 264a 7000 nop
4242 84: 077c ffe1 beq.d -132
43- 88: 264a 7000 mov 0,0
43+ 88: 264a 7000 nop
4444 8c: 0774 ffc2 bne -140
4545 90: 0770 ffe6 bnc.d -144
46- 94: 264a 7000 mov 0,0
46+ 94: 264a 7000 nop
--- a/gas/testsuite/gas/arc/noargs_hs.d
+++ b/gas/testsuite/gas/arc/noargs_hs.d
@@ -14,7 +14,7 @@ Disassembly of section .text:
1414 e: 246f 003f rtie
1515 12: 216f 003f sleep 0
1616 16: 226f 103f dsync
17- 1a: 264a 7000 mov 0,0
17+ 1a: 264a 7000 nop
1818 1e: 78e0 nop_s
1919 20: 256f 003f brk
2020 24: 236f 003f sync
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
1+2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
2+
3+ * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
4+
15 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
26
37 * mips-dis.c (print_mips_disassembler_options): Add
--- a/opcodes/arc-tbl.h
+++ b/opcodes/arc-tbl.h
@@ -10113,6 +10113,9 @@
1011310113 /* minidl<.f><.cc> 0,limm,limm 0010111011001001F1111111100QQQQQ. */
1011410114 { "minidl", 0x2EC97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
1011510115
10116+/* nop 00100110010010100111000000000000. */
10117+{ "nop", 0x264A7000, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
10118+
1011610119 /* mov<.f> b,c 00100bbb00001010FBBBCCCCCCRRRRRR. */
1011710120 { "mov", 0x200A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { RB, RC }, { C_F }},
1011810121
@@ -12702,9 +12705,6 @@
1270212705 /* neg_s b,c 01111bbbccc10011. */
1270312706 { "neg_s", 0x00007813, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }},
1270412707
12705-/* nop 00100110010010100111000000000000. */
12706-{ "nop", 0x264A7000, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
12707-
1270812708 /* nop_s 0111100011100000. */
1270912709 { "nop_s", 0x000078E0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
1271012710