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GNU Binutils with patches for OS216


コミットメタ情報

リビジョン07f5af7d3c635234284e7a0f7dd7a410b1628b8b (tree)
日時2016-06-04 07:55:29
作者H.J. Lu <hjl.tools@gmai...>
コミッターH.J. Lu

ログメッセージ

Handle indirect branches for AMD64 and Intel64

AMD64 spec and Intel64 spec differ in indirect branches in 64-bit mode.
AMD64 supports indirect branches with 16-bit address via the data size
prefix while the data size prefix is ignored by Intel64.

gas/

PR binutis/18386
* testsuite/gas/i386/i386.exp: Run x86-64-branch-4.
* testsuite/gas/i386/x86-64-branch.d: Updated.
* testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise.
* testsuite/gas/i386/x86-64-branch-4.l: New file.
* testsuite/gas/i386/x86-64-branch-4.s: Likewise.

opcodes/

PR binutis/18386
* i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
(indir_v_mode): New.
Add comments for '&'.
(reg_table): Replace "{T|}" with "{&|}" on call and jmp.
(putop): Handle '&'.
(intel_operand_size): Handle indir_v_mode.
(OP_E_register): Likewise.
* i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
64-bit indirect call/jmp for AMD64.
* i386-tbl.h: Regenerated

変更サマリ

差分

--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
1+2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
2+
3+ PR binutis/18386
4+ * testsuite/gas/i386/i386.exp: Run x86-64-branch-4.
5+ * testsuite/gas/i386/x86-64-branch.d: Updated.
6+ * testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise.
7+ * testsuite/gas/i386/x86-64-branch-4.l: New file.
8+ * testsuite/gas/i386/x86-64-branch-4.s: Likewise.
9+
110 2016-06-03 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
211
312 * config/tc-aarch64.c (aarch64_cpus): Add cortex-a73 entry.
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -816,6 +816,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
816816 run_dump_test "x86-64-jump"
817817 run_dump_test "x86-64-branch-2"
818818 run_list_test "x86-64-branch-3" "-al -mintel64"
819+ run_list_test "x86-64-branch-4" "-al -mintel64"
819820
820821 run_dump_test "x86-64-gotpcrel"
821822 run_dump_test "x86-64-gotpcrel-no-relax"
--- a/gas/testsuite/gas/i386/ilp32/x86-64-branch.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-branch.d
@@ -10,14 +10,14 @@ Disassembly of section .text:
1010 0+ <.text>:
1111 [ ]*[a-f0-9]+: ff d0 callq \*%rax
1212 [ ]*[a-f0-9]+: ff d0 callq \*%rax
13-[ ]*[a-f0-9]+: 66 ff d0 callw \*%ax
14-[ ]*[a-f0-9]+: 66 ff d0 callw \*%ax
15-[ ]*[a-f0-9]+: 66 ff 10 callw \*\(%rax\)
13+[ ]*[a-f0-9]+: 66 ff d0 data16 callq \*%rax
14+[ ]*[a-f0-9]+: 66 ff d0 data16 callq \*%rax
15+[ ]*[a-f0-9]+: 66 ff 10 data16 callq \*\(%rax\)
1616 [ ]*[a-f0-9]+: ff e0 jmpq \*%rax
1717 [ ]*[a-f0-9]+: ff e0 jmpq \*%rax
18-[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
19-[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
20-[ ]*[a-f0-9]+: 66 ff 20 jmpw \*\(%rax\)
18+[ ]*[a-f0-9]+: 66 ff e0 data16 jmpq \*%rax
19+[ ]*[a-f0-9]+: 66 ff e0 data16 jmpq \*%rax
20+[ ]*[a-f0-9]+: 66 ff 20 data16 jmpq \*\(%rax\)
2121 [ ]*[a-f0-9]+: e8 00 00 00 00 callq 0x1f 1b: R_X86_64_PC32 \*ABS\*\+0x10003c
2222 [ ]*[a-f0-9]+: e9 00 00 00 00 jmpq 0x24 20: R_X86_64_PC32 \*ABS\*\+0x10003c
2323 [ ]*[a-f0-9]+: 66 e8 00 00 00 00 data16 callq 0x2a 26: R_X86_64_PC32 foo-0x4
@@ -25,14 +25,14 @@ Disassembly of section .text:
2525 [ ]*[a-f0-9]+: 66 0f 82 00 00 00 00 data16 jb 0x37 33: R_X86_64_PC32 foo-0x4
2626 [ ]*[a-f0-9]+: ff d0 callq \*%rax
2727 [ ]*[a-f0-9]+: ff d0 callq \*%rax
28-[ ]*[a-f0-9]+: 66 ff d0 callw \*%ax
29-[ ]*[a-f0-9]+: 66 ff d0 callw \*%ax
30-[ ]*[a-f0-9]+: 66 ff 10 callw \*\(%rax\)
28+[ ]*[a-f0-9]+: 66 ff d0 data16 callq \*%rax
29+[ ]*[a-f0-9]+: 66 ff d0 data16 callq \*%rax
30+[ ]*[a-f0-9]+: 66 ff 10 data16 callq \*\(%rax\)
3131 [ ]*[a-f0-9]+: ff e0 jmpq \*%rax
3232 [ ]*[a-f0-9]+: ff e0 jmpq \*%rax
33-[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
34-[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
35-[ ]*[a-f0-9]+: 66 ff 20 jmpw \*\(%rax\)
33+[ ]*[a-f0-9]+: 66 ff e0 data16 jmpq \*%rax
34+[ ]*[a-f0-9]+: 66 ff e0 data16 jmpq \*%rax
35+[ ]*[a-f0-9]+: 66 ff 20 data16 jmpq \*\(%rax\)
3636 [ ]*[a-f0-9]+: e8 00 00 00 00 callq 0x56 52: R_X86_64_PC32 \*ABS\*\+0x10003c
3737 [ ]*[a-f0-9]+: e9 00 00 00 00 jmpq 0x5b 57: R_X86_64_PC32 \*ABS\*\+0x10003c
3838 #pass
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-branch-4.l
@@ -0,0 +1,33 @@
1+.*: Assembler messages:
2+.*:2: Error: invalid instruction suffix for `call'
3+.*:3: Error: invalid instruction suffix for `call'
4+.*:4: Error: operand type mismatch for `jmp'
5+.*:5: Error: invalid instruction suffix for `jmp'
6+.*:6: Error: invalid instruction suffix for `jmp'
7+.*:9: Error: operand type mismatch for `call'
8+.*:10: Error: invalid instruction suffix for `call'
9+.*:11: Error: invalid instruction suffix for `call'
10+.*:12: Error: invalid instruction suffix for `call'
11+.*:13: Error: operand type mismatch for `jmp'
12+.*:14: Error: invalid instruction suffix for `jmp'
13+.*:15: Error: invalid instruction suffix for `jmp'
14+.*:16: Error: invalid instruction suffix for `jmp'
15+GAS LISTING .*
16+#...
17+[ ]*1[ ]+\.text
18+[ ]*2[ ]+callw \*%ax
19+[ ]*3[ ]+callw \*\(%rax\)
20+[ ]*4[ ]+jmp \*%ax
21+[ ]*5[ ]+jmpw \*%ax
22+[ ]*6[ ]+jmpw \*\(%rax\)
23+[ ]*7[ ]+
24+[ ]*8[ ]+\.intel_syntax noprefix
25+[ ]*9[ ]+call ax
26+[ ]*10[ ]+callw ax
27+[ ]*11[ ]+callw \[rax\]
28+[ ]*12[ ]+call WORD PTR \[rax\]
29+[ ]*13[ ]+jmp ax
30+[ ]*14[ ]+jmpw ax
31+[ ]*15[ ]+jmpw \[rax\]
32+[ ]*16[ ]+jmp WORD PTR \[rax\]
33+#pass
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-branch-4.s
@@ -0,0 +1,16 @@
1+.text
2+ callw *%ax
3+ callw *(%rax)
4+ jmp *%ax
5+ jmpw *%ax
6+ jmpw *(%rax)
7+
8+ .intel_syntax noprefix
9+ call ax
10+ callw ax
11+ callw [rax]
12+ call WORD PTR [rax]
13+ jmp ax
14+ jmpw ax
15+ jmpw [rax]
16+ jmp WORD PTR [rax]
--- a/gas/testsuite/gas/i386/x86-64-branch.d
+++ b/gas/testsuite/gas/i386/x86-64-branch.d
@@ -9,14 +9,14 @@ Disassembly of section .text:
99 0+ <.text>:
1010 [ ]*[a-f0-9]+: ff d0 callq \*%rax
1111 [ ]*[a-f0-9]+: ff d0 callq \*%rax
12-[ ]*[a-f0-9]+: 66 ff d0 callw \*%ax
13-[ ]*[a-f0-9]+: 66 ff d0 callw \*%ax
14-[ ]*[a-f0-9]+: 66 ff 10 callw \*\(%rax\)
12+[ ]*[a-f0-9]+: 66 ff d0 data16 callq \*%rax
13+[ ]*[a-f0-9]+: 66 ff d0 data16 callq \*%rax
14+[ ]*[a-f0-9]+: 66 ff 10 data16 callq \*\(%rax\)
1515 [ ]*[a-f0-9]+: ff e0 jmpq \*%rax
1616 [ ]*[a-f0-9]+: ff e0 jmpq \*%rax
17-[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
18-[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
19-[ ]*[a-f0-9]+: 66 ff 20 jmpw \*\(%rax\)
17+[ ]*[a-f0-9]+: 66 ff e0 data16 jmpq \*%rax
18+[ ]*[a-f0-9]+: 66 ff e0 data16 jmpq \*%rax
19+[ ]*[a-f0-9]+: 66 ff 20 data16 jmpq \*\(%rax\)
2020 [ ]*[a-f0-9]+: e8 (00|5b) 00 (00|10) 00 callq (0x1f|10007a <.text\+0x10007a>)
2121 [ ]*[a-f0-9]+: e9 (00|60) 00 (00|10) 00 jmpq (0x24|100084 <.text\+0x100084>)
2222 [ ]*[a-f0-9]+: 66 e8 00 00 00 00 data16 callq (0x2a|2a <.text\+0x2a>)
@@ -24,14 +24,14 @@ Disassembly of section .text:
2424 [ ]*[a-f0-9]+: 66 0f 82 00 00 00 00 data16 jb (0x37|37 <.text\+0x37>)
2525 [ ]*[a-f0-9]+: ff d0 callq \*%rax
2626 [ ]*[a-f0-9]+: ff d0 callq \*%rax
27-[ ]*[a-f0-9]+: 66 ff d0 callw \*%ax
28-[ ]*[a-f0-9]+: 66 ff d0 callw \*%ax
29-[ ]*[a-f0-9]+: 66 ff 10 callw \*\(%rax\)
27+[ ]*[a-f0-9]+: 66 ff d0 data16 callq \*%rax
28+[ ]*[a-f0-9]+: 66 ff d0 data16 callq \*%rax
29+[ ]*[a-f0-9]+: 66 ff 10 data16 callq \*\(%rax\)
3030 [ ]*[a-f0-9]+: ff e0 jmpq \*%rax
3131 [ ]*[a-f0-9]+: ff e0 jmpq \*%rax
32-[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
33-[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
34-[ ]*[a-f0-9]+: 66 ff 20 jmpw \*\(%rax\)
32+[ ]*[a-f0-9]+: 66 ff e0 data16 jmpq \*%rax
33+[ ]*[a-f0-9]+: 66 ff e0 data16 jmpq \*%rax
34+[ ]*[a-f0-9]+: 66 ff 20 data16 jmpq \*\(%rax\)
3535 [ ]*[a-f0-9]+: e8 (00|92) 00 (00|10) 00 callq (0x56|1000e8 <.text\+0x1000e8>)
3636 [ ]*[a-f0-9]+: e9 (00|97) 00 (00|10) 00 jmpq (0x5b|1000f2 <.text\+0x1000f2>)
3737 #pass
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,17 @@
1+2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
2+
3+ PR binutis/18386
4+ * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
5+ (indir_v_mode): New.
6+ Add comments for '&'.
7+ (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
8+ (putop): Handle '&'.
9+ (intel_operand_size): Handle indir_v_mode.
10+ (OP_E_register): Likewise.
11+ * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
12+ 64-bit indirect call/jmp for AMD64.
13+ * i386-tbl.h: Regenerated
14+
115 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
216
317 * arc-dis.c (struct arc_operand_iterator): New structure.
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -258,7 +258,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
258258 #define Edw { OP_E, dw_mode }
259259 #define Edqd { OP_E, dqd_mode }
260260 #define Eq { OP_E, q_mode }
261-#define indirEv { OP_indirE, stack_v_mode }
261+#define indirEv { OP_indirE, indir_v_mode }
262262 #define indirEp { OP_indirE, f_mode }
263263 #define stackEv { OP_E, stack_v_mode }
264264 #define Em { OP_E, m_mode }
@@ -561,6 +561,8 @@ enum
561561 /* 4- or 6-byte pointer operand */
562562 f_mode,
563563 const_1_mode,
564+ /* v_mode for indirect branch opcodes. */
565+ indir_v_mode,
564566 /* v_mode for stack-related opcodes. */
565567 stack_v_mode,
566568 /* non-quad operand size depends on prefixes */
@@ -2483,6 +2485,9 @@ struct dis386 {
24832485 suffix_always is true (lcall/ljmp).
24842486 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
24852487 on operand size prefix.
2488+ '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2489+ has no operand size prefix for AMD64 ISA, behave as 'P'
2490+ otherwise
24862491
24872492 2 upper case letter macros:
24882493 "XY" => print 'x' or 'y' if suffix_always is true or no register
@@ -3531,9 +3536,9 @@ static const struct dis386 reg_table[][8] = {
35313536 {
35323537 { "incQ", { Evh1 }, 0 },
35333538 { "decQ", { Evh1 }, 0 },
3534- { "call{T|}", { indirEv, BND }, 0 },
3539+ { "call{&|}", { indirEv, BND }, 0 },
35353540 { MOD_TABLE (MOD_FF_REG_3) },
3536- { "jmp{T|}", { indirEv, BND }, 0 },
3541+ { "jmp{&|}", { indirEv, BND }, 0 },
35373542 { MOD_TABLE (MOD_FF_REG_5) },
35383543 { "pushU", { stackEv }, 0 },
35393544 { Bad_Opcode },
@@ -14296,6 +14301,15 @@ case_L:
1429614301 if (!(rex & REX_W))
1429714302 used_prefixes |= (prefixes & PREFIX_DATA);
1429814303 break;
14304+ case '&':
14305+ if (!intel_syntax
14306+ && address_mode == mode_64bit
14307+ && isa64 == intel64)
14308+ {
14309+ *obufp++ = 'q';
14310+ break;
14311+ }
14312+ /* Fall through. */
1429914313 case 'T':
1430014314 if (!intel_syntax
1430114315 && address_mode == mode_64bit
@@ -14816,6 +14830,12 @@ intel_operand_size (int bytemode, int sizeflag)
1481614830 case dqw_swap_mode:
1481714831 oappend ("WORD PTR ");
1481814832 break;
14833+ case indir_v_mode:
14834+ if (address_mode == mode_64bit && isa64 == intel64)
14835+ {
14836+ oappend ("QWORD PTR ");
14837+ break;
14838+ }
1481914839 case stack_v_mode:
1482014840 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
1482114841 {
@@ -15193,6 +15213,12 @@ OP_E_register (int bytemode, int sizeflag)
1519315213 case bnd_mode:
1519415214 names = names_bnd;
1519515215 break;
15216+ case indir_v_mode:
15217+ if (address_mode == mode_64bit && isa64 == intel64)
15218+ {
15219+ names = names64;
15220+ break;
15221+ }
1519615222 case stack_v_mode:
1519715223 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
1519815224 {
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -322,7 +322,8 @@ call, 1, 0xe8, None, 1, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|N
322322 call, 1, 0xe8, None, 1, Cpu64, AMD64|JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Disp16|Disp32S }
323323 call, 1, 0xe8, None, 1, Cpu64, Intel64|JumpDword|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Disp32S }
324324 call, 1, 0xff, 0x2, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|JumpAbsolute }
325-call, 1, 0xff, 0x2, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute }
325+call, 1, 0xff, 0x2, 1, Cpu64, AMD64|Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute }
326+call, 1, 0xff, 0x2, 1, Cpu64, Intel64|Modrm|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute }
326327 // Intel Syntax
327328 call, 2, 0x9a, None, 1, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
328329 // Intel Syntax
@@ -334,7 +335,8 @@ jmp, 1, 0xeb, None, 1, CpuNo64, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_
334335 jmp, 1, 0xeb, None, 1, Cpu64, AMD64|Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32S }
335336 jmp, 1, 0xeb, None, 1, Cpu64, Intel64|Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp32S }
336337 jmp, 1, 0xff, 0x4, 1, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|JumpAbsolute }
337-jmp, 1, 0xff, 0x4, 1, Cpu64, Modrm|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute }
338+jmp, 1, 0xff, 0x4, 1, Cpu64, AMD64|Modrm|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute }
339+jmp, 1, 0xff, 0x4, 1, Cpu64, Intel64|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute }
338340 // Intel Syntax.
339341 jmp, 2, 0xea, None, 1, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
340342 // Intel Syntax.
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -3230,10 +3230,23 @@ const insn_template i386_optab[] =
32303230 { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0,
32313231 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
32323232 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3233- 0, 0, 0, 0 },
3233+ 0, 0, 1, 0 },
32343234 { { { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
32353235 0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0,
32363236 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } },
3237+ { "call", 1, 0xff, 0x2, 1,
3238+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3239+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3240+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3241+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3242+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
3243+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
3244+ 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
3245+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3246+ 0, 0, 0, 1 },
3247+ { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3248+ 0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
3249+ 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } },
32373250 { "call", 2, 0x9a, None, 1,
32383251 { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
32393252 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -3353,10 +3366,23 @@ const insn_template i386_optab[] =
33533366 { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
33543367 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
33553368 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3356- 0, 0, 0, 0 },
3369+ 0, 0, 1, 0 },
33573370 { { { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
33583371 0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0,
33593372 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } },
3373+ { "jmp", 1, 0xff, 0x4, 1,
3374+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3375+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3376+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3377+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3378+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
3379+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,
3380+ 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
3381+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3382+ 0, 0, 0, 1 },
3383+ { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3384+ 0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
3385+ 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } },
33603386 { "jmp", 2, 0xea, None, 1,
33613387 { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
33623388 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,