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client (0.6.2 anago only)2010-11-19 20:00
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Flash Memory Cartridge - Software Terminology

command addresses

In order to successfully send a command, the bus will need to send write commands to the following 3 addresses in sequential order: 0x2aaa, 0x5555, and programming address.

example 1: MMC3

Configure CPU memory bank on MMC3:

 cpu address|rom address    |page|task
 $8000-$9fff|0x02000-0x03fff|1   |write 0x2aaa
 $a000-$bfff|n * 0x2000     |n   |write area
 $c000-$ffff|0x7c000-0x7ffff|fix |write 0x5555, boot area

When switching the CPU bank to page 1 on $8000-0x9fff, the command address 0x2aaa appears on $8aaa. 0x5555 is also placed on a fixed-area, $d555. Finally, programming address is used on $a000-$bfff. Which area is translated ROM image with bank switching.

Once configuration is finished, the bus will request an erasing command, followed by the actual flash programming. Configuration should be simple if the CPU bank has 3 areas.

 ppu address|rom address    |page|task
 $0000-$07ff|0x02800-0x02fff|0x0a|write 0x2aaa
 $0800-$0fff|0x05000-0x057ff|0x14|write 0x5555
 $1000-$1fff|n * 0x1000     |n   |write area

Since the PPU region's bank size is smaller compared to the CPU, calculating page numbers for command addresses will take a while.

example 2: MMC1 SLROM

MMC1 has two two CPU banks. In this case, the bus secures command addresses and the programming area in an even/odd interleaved order.

 cpu address|rom address    |page|task
 $8000-$bfff|n * 0x4000     |even|write 0x2aaa + write area
 $c000-$ffff|0x3c000-0x3ffff|fix |write 0x5555

First, the "even" addresses are transferred.

 cpu address|rom address    |page|task
 $8000-$bfff|0x00000-0x03fff|fix |write 0x2aaa
 $c000-$ffff|n * 0x4000     |odd |write 0x5555 + write area

Then, the "odd" addresses follow.

MMC1 has two PPU banks as well. But unlike the previous command addresses, 0x2aaa and 0x5555 are programmed together in the first bank. Please keep in mind that programming character memory for MMC1 is only possible for command address A0-A10 style flash memory. A0-A14 style flash is incompatible.

 ppu address|rom address    |page|task
 $0000-$0fff|0x00000 * n    |n   |write area + 0x2aa + 0x555
 $0000-$1fff|0x01000 * n    |n+1 |write area
Even though the previous directions imply writing for A0-A14 flash, this also applies for A0-A10 flash.