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リビジョンf904c03d58e3f7230bdaadc2b4c42ac670ed2e70 (tree)
日時2013-05-30 14:53:56
作者naruko <naruko@24ea...>
コミッターnaruko

ログメッセージ

cartrdige script を管理開始 (なぜかやってなかった)

git-svn-id: svn+ssh://svn.osdn.net/svnroot/unagi@410 24ea1065-a21e-4ca1-99c9-f5125deb0858

変更サマリ

差分

--- /dev/null
+++ b/client/trunk/anago/bandai_fcg1.ad
@@ -0,0 +1,32 @@
1+/*
2+BANDAI FCG-1, FCG-2
3+FCG-1 + Program ROM + Charcter ROM
4+ ドラゴンボール 大魔王復活
5+ 西村京太郎ミステリー ブルートレイン殺人事件 (Irem)
6+FCG-2 + Program ROM + Charcter ROM
7+ ファミコンジャンプ
8+ 魁!!男塾
9+ 名門!第三野球部
10+ ドラゴンボール3
11+ 悪魔くん
12+*/
13+board <- {
14+ mappernum = 16,
15+ cpu_rom = {
16+ size_base = 2 * mega, size_max = 2 * mega,
17+ banksize = 0x4000
18+ },
19+ cpu_ram = {
20+ size_base = 0x0000, size_max = 0x0000,
21+ banksize = 0x2000
22+ },
23+ ppu_rom = {
24+ size_base = 2 * mega, size_max = 2 * mega,
25+ banksize = 0x0400
26+ },
27+ ppu_ramfind = false,
28+ vram_mirrorfind = false
29+};
30+
31+const register_offset = 0x6000;
32+dofile("fcg3.ai");
--- /dev/null
+++ b/client/trunk/anago/bandai_fcg3_x24c01.ag
@@ -0,0 +1,95 @@
1+/*
2+BANDAI FCG-3 + X24C01 style cartridge
3+
4+SDガンダム外伝 ナイトガンダム物語
5+ 1990-08-11 B50EEP, LZ93D50+X24C01
6+ドラゴンボールZ 強襲!サイヤ人
7+ 1990-10-27 DRAGON BALLZ, LZ93D50+X24C01
8+まじかる☆タルるートくん ファンタスティックワールド
9+ 1991-03-21 DRAGON BALLZ-B, LZ93D50+X24C01
10+まじかる☆タルるートくん2
11+ 1992-06-19 DRAGON BALLZ-B, LZ93D50+X24C01 ← 24C02 ではない
12+*/
13+board <- {
14+ mappernum = 16,
15+ cpu_rom = {
16+ size_base = 2 * mega, size_max = 2 * mega,
17+ banksize = 0x4000
18+ },
19+ cpu_ram = {
20+ size_base = 0x0080, size_max = 0x0080,
21+ banksize = 0x0080
22+ },
23+ ppu_rom = {
24+ size_base = 1 * mega, size_max = 2 * mega,
25+ banksize = 0x0400
26+ },
27+ ppu_ramfind = false,
28+ vram_mirrorfind = false
29+};
30+
31+const register_offset = 0x8000;
32+dofile("fcg3.ai");
33+
34+/*
35+=====================
36+X24C01 frame sequence
37+=====================
38+<START>[EEPROM address+RW]<A-ACK>[data]<D-ACK><STOP>
39+
40+<> is 1bit, [] is 8bit, A-ACK is address acknowledge,
41+D-ACK is data acknowledge, R is 1, W is 0
42+
43+8bit data send MSB to LSB (bit7 to bit0)
44+Dragon Ball Z1's program send address LSB to MSB (bug).
45+
46+slave address does not exist.
47+
48+--current address read--
49+<START>[EEPROM address,R]<A-ACK>[EEPROM data]<D-ACK><STOP>
50+
51+--sequenctial read--
52+<START>[EEPROM address,R]<A-ACK>|[EEPROM data]<D-ACK>|<STOP>
53+ |<- loop any times ->|
54+
55+--page write---
56+|<START>[EEPROM address,W]<A-ACK>|[EEPROM data]<D-ACK>|<STOP>
57+|<- loop A-ACK is H ->|<- loop 1to4times ->|
58+*/
59+
60+function cpu_ram_access(d, pagesize, banksize)
61+{
62+ local I2C_WRITE = I2C_SEND_L;
63+ local I2C_READ = I2C_SEND_H;
64+
65+ if(mode_is_read(d) == true){
66+ //sequential read
67+ i2c_address_set(d, 0, I2C_READ);
68+ for(local i = 0; i < pagesize * banksize; i++){
69+ for(local bit = 0; bit < 8; bit++){
70+ cpu_write(d, 0x800d, I2C_DIR_WRITE | I2C_CLOCK_L | I2C_SEND_H);
71+ cpu_write(d, 0x800d, I2C_DIR_READ | I2C_CLOCK_H | I2C_SEND_H);
72+ cpu_read_bit_msb(d, 0x6000, 4);
73+ }
74+ //send ack
75+ send_bit(d, I2C_SEND_L);
76+ }
77+ i2c_stop(d);
78+ }else{
79+ //page write (4byte)
80+ for(local i = 0; i < pagesize * banksize; i+=4){
81+ i2c_address_set(d, i, I2C_WRITE);
82+ for(local j = 0; j < 4; j++){
83+ for(local bit = 0; bit < 8; bit++){
84+ local n = I2C_SEND_L;
85+ if(cpu_fetch_bit_msb(d) != 0){
86+ n = I2C_SEND_H;
87+ }
88+ send_bit(d, n);
89+ }
90+ i2c_ack_wait(d);
91+ }
92+ i2c_stop(d);
93+ }
94+ }
95+}
--- /dev/null
+++ b/client/trunk/anago/bandai_fcg3_x24c02.ag
@@ -0,0 +1,113 @@
1+/*
2+BANDAI FCG-3 + X24C02 style cartridge
3+
4+ドラゴンボールZII 激神フリーザ!!
5+ 1991-08-10, DRAGON BALLZ-B ,LZ93D50+X24C02
6+SDガンダム外伝 ナイトガンダム物語2
7+ 1991-10-12, DRAGON BALLZ-B, LZ93D50+X24C02
8+SDガンダム外伝 ナイトガンダム物語3
9+ 1992-10-23, DRAGON BALLZ-B, LZ93D50+X24C02
10+DATACH 本体
11+ 1992-12-19, BA-BAR, LZ93D50P+X24C02 (Charcter RAM)
12+クレヨンしんちゃん
13+ 1993-08-27, DRAGON BALLZ-B, LZ93D50 (EEPROM なし)
14+ろくでなしBLUES
15+ 1993-10-29, DRAGON BALLZ-B, LZ93D50+X24C02
16+*/
17+board <- {
18+ mappernum = 16,
19+ cpu_rom = {
20+ size_base = 2 * mega, size_max = 2 * mega,
21+ banksize = 0x4000
22+ },
23+ cpu_ram = {
24+ size_base = 0x0100, size_max = 0x0100,
25+ banksize = 0x0100
26+ },
27+ ppu_rom = {
28+ size_base = 2 * mega, size_max = 2 * mega,
29+ banksize = 0x0400
30+ },
31+ ppu_ramfind = true,
32+ vram_mirrorfind = false
33+};
34+
35+const register_offset = 0x8000;
36+dofile("fcg3.ai")
37+/*
38+=====================
39+X24C02 frame sequence
40+=====================
41+<START>[slave address+RW]<A-ACK>[data]<D-ACK><STOP>
42+
43+<> is 1bit, [] is 8bit, A-ACK is address acknowledge,
44+D-ACK is data acknowledge, R is 1, W is 0
45+
46+slave address 6:3 is 4'b0101, fixed
47+slave address 2:0 is 3'b000, configurated by PCB
48+
49+8bit data send MSB to LSB (bit7 to bit0)
50+
51+--current address set--
52+<START>[0x50,W]<A-ACK>[EEPROM address]<D-ACK><STOP>
53+
54+--current address read--
55+<START>[0x50,R]<A-ACK>[EEPROM data]<D-ACK><STOP>
56+
57+--sequenctial read--
58+<START>[0x50,R]<A-ACK>|[EEPROM data]<D-ACK>|<STOP>
59+ |<- loop any times ->|
60+
61+after read operation, EEPROM address is incremented
62+
63+--page write---
64+|<START>[0x50,W]<A-ACK>|[EEPROM address]<D-ACK>|[EEPROM data]<D-ACK>|<STOP>
65+|<- loop A-ACK is H ->| |<- loop 1to4times ->|
66+
67+After write operation, EEPROM controller is writing data, time is required of 2ms.
68+duaring polling, A-ACK returns H. Retry operation.
69+
70+The page write count is different by the manufacturer.
71+X24C01 and X24C02 are designed page write count is 4.
72+*/
73+function cpu_ram_access(d, pagesize, banksize)
74+{
75+ local I2C_WRITE = I2C_SEND_L;
76+ local I2C_READ = I2C_SEND_H;
77+
78+ if(mode_is_read(d) == true){
79+ //sequenctial read
80+ i2c_address_set(d, 0x50, I2C_WRITE);
81+ eeprom_address_set(d, 0);
82+
83+ i2c_address_set(d, 0x50, I2C_READ);
84+ for(local i = 0; i < pagesize * banksize; i++){
85+ for(local bit = 0; bit < 8; bit++){
86+ cpu_write(d, 0x800d, I2C_DIR_WRITE | I2C_CLOCK_L | I2C_SEND_H);
87+ cpu_write(d, 0x800d, I2C_DIR_READ | I2C_CLOCK_H | I2C_SEND_H);
88+ cpu_read_bit_msb(d, 0x6000, 4);
89+ }
90+ //send ack
91+ send_bit(d, I2C_SEND_L);
92+ }
93+ i2c_stop(d);
94+ }else{
95+ //page write. 4byte
96+ for(local i = 0; i < pagesize * banksize; i+=4){
97+ i2c_address_set(d, 0x50, I2C_WRITE);
98+ eeprom_address_set(d, i);
99+ for(local j = 0; j < 4; j++){
100+ for(local bit = 0; bit < 8; bit++){
101+ local n = I2C_SEND_L;
102+ if(cpu_fetch_bit_msb(d) != 0){
103+ n = I2C_SEND_H;
104+ }
105+ send_bit(d, n);
106+ }
107+ i2c_ack_wait(d);
108+ }
109+ i2c_stop(d);
110+ }
111+ }
112+
113+}
--- /dev/null
+++ b/client/trunk/anago/cnrom.af
@@ -0,0 +1,51 @@
1+board <- {
2+ mappernum = 3,
3+ cpu_rom = {
4+ size_base = 0x8000, size_max = 0x8000
5+ banksize = 0x8000
6+ },
7+ ppu_rom= {
8+ size_base = 0x8000, size_max = 0x8000,
9+ banksize = 0x2000
10+ },
11+ ppu_ramfind = false, vram_mirrorfind = true
12+};
13+function cpu_dump(d, pagesize, banksize)
14+{
15+ cpu_read(d, 0x8000, 0x4000);
16+ cpu_read(d, 0xc000, 0x4000);
17+}
18+function ppu_dump(d, pagesize, banksize)
19+{
20+ for(local i = 0; i < pagesize; i++){
21+ cpu_write(d, 0x8000, 0xf0 | i);
22+ ppu_read(d, 0, banksize);
23+ }
24+}
25+
26+function program_initalize(d, cpu_banksize, ppu_banksize)
27+{
28+ cpu_write(d, 0x8000, 0x30);
29+ cpu_command(d, 0, 0x8000, cpu_banksize);
30+ cpu_command(d, 0x02aa, 0xc000, cpu_banksize);
31+ cpu_command(d, 0x0555, 0xc000, cpu_banksize);
32+ ppu_command(d, 0, 0x0000, ppu_banksize);
33+ ppu_command(d, 0x02aa, 0x0000, ppu_banksize);
34+ ppu_command(d, 0x0555, 0x0000, ppu_banksize);
35+}
36+
37+function cpu_transfer(d, start, end, cpu_banksize)
38+{
39+ if(cpu_banksize == 0x8000){
40+ cpu_program(d, 0x8000, 0x4000);
41+ }
42+ cpu_program(d, 0xc000, 0x4000);
43+}
44+
45+function ppu_transfer(d, start, end, ppu_banksize)
46+{
47+ for(local i = start; i < end; i++){
48+ cpu_write(d, 0x8000, 0xf0 | i);
49+ ppu_program(d, 0x0000, ppu_banksize);
50+ }
51+}
--- /dev/null
+++ b/client/trunk/anago/fcg3.ai
@@ -0,0 +1,130 @@
1+//cpu_dump, ppu_dump 内で同名の関数を呼んではいけない
2+function cpu_dump(d, pagesize, banksize)
3+{
4+
5+ for(local i = 0; i < pagesize - 1; i += 1){
6+ cpu_write(d, register_offset + 8, i);
7+ cpu_read(d, 0x8000, banksize);
8+ }
9+ cpu_read(d, 0xc000, banksize);
10+}
11+
12+function ppu_dump(d, pagesize, banksize)
13+{
14+ for(local i = 0; i < pagesize; i += 8){
15+ for(local j = 0; j < 8; j += 1){
16+ cpu_write(d, register_offset + j, i + j);
17+ ppu_read(d, j * banksize, banksize);
18+ }
19+ }
20+}
21+
22+function program_initalize(d, cpu_banksize, ppu_banksize)
23+{
24+ cpu_write(d, 0x8008, 0x00);
25+ cpu_command(d, 0x0000, 0x8000, cpu_banksize);
26+ cpu_command(d, 0x02aa, 0xc000, cpu_banksize);
27+ cpu_command(d, 0x0555, 0xc000, cpu_banksize);
28+ cpu_write(d, 0x8000, [0x0a, 0x15, 0]);
29+ ppu_command(d, 0x2aaa, 0, ppu_banksize);
30+ ppu_command(d, 0x5555, 0x0400, ppu_banksize);
31+ ppu_command(d, 0, 0x0800, ppu_banksize);
32+}
33+
34+function cpu_transfer(d, start, end, cpu_banksize)
35+{
36+ for(local i = start; i < end - 1; i +=1){
37+ cpu_write(d, 0x8008, i);
38+ cpu_program(d, 0x8000, cpu_banksize);
39+ }
40+ cpu_program(d, 0xc000, cpu_banksize);
41+}
42+
43+function ppu_transfer(d, start, end, ppu_banksize)
44+{
45+ for(local i = start; i < end; i +=4){
46+ cpu_write(d, 0x8004, [i, i+1, i+2, i+3]);
47+ ppu_program(d, 0x1000, ppu_banksize * 4);
48+ }
49+}
50+/*
51+$800d
52+7 data direction 0:FCG3->EEPROM (write), 1:EEPROM->FCG3 (read)
53+6 data, FCG3 -> EEPROM
54+5 clock
55+
56+$6000-$7fff
57+4 data, EEPROM -> FCG3
58+*/
59+const I2C_READBIT = 4;
60+const I2C_DIRBIT = 7;
61+const I2C_WRITEBIT = 6;
62+const I2C_CLOCKBIT = 5;
63+
64+I2C_DIR_READ <- 1 << I2C_DIRBIT;
65+I2C_DIR_WRITE <- 0 << I2C_DIRBIT;
66+I2C_SEND_H <- 1 << I2C_WRITEBIT;
67+I2C_SEND_L <- 0 << I2C_WRITEBIT;
68+I2C_CLOCK_H <- 1 << I2C_CLOCKBIT;
69+I2C_CLOCK_L <- 0 << I2C_CLOCKBIT;
70+
71+function i2c_start(d)
72+{
73+ cpu_write(d, 0x800d, I2C_DIR_WRITE | I2C_CLOCK_L | I2C_SEND_L);
74+ cpu_write(d, 0x800d, I2C_DIR_WRITE | I2C_CLOCK_L | I2C_SEND_H);
75+ cpu_write(d, 0x800d, I2C_DIR_WRITE | I2C_CLOCK_H | I2C_SEND_H);
76+ cpu_write(d, 0x800d, I2C_DIR_WRITE | I2C_CLOCK_H | I2C_SEND_L);
77+ cpu_write(d, 0x800d, I2C_DIR_WRITE | I2C_CLOCK_L | I2C_SEND_L);
78+}
79+
80+function i2c_stop(d)
81+{
82+ cpu_write(d, 0x800d, I2C_DIR_WRITE | I2C_CLOCK_L | I2C_SEND_L);
83+ cpu_write(d, 0x800d, I2C_DIR_WRITE | I2C_CLOCK_H | I2C_SEND_L);
84+ cpu_write(d, 0x800d, I2C_DIR_WRITE | I2C_CLOCK_H | I2C_SEND_H);
85+ cpu_write(d, 0x800d, I2C_DIR_WRITE | I2C_CLOCK_L | I2C_SEND_H);
86+ cpu_write(d, 0x800d, I2C_DIR_READ | I2C_CLOCK_L | I2C_SEND_H);
87+}
88+
89+function i2c_ack_wait(d)
90+{
91+ cpu_write(d, 0x800d, I2C_DIR_WRITE | I2C_CLOCK_L | I2C_SEND_H);
92+ cpu_write(d, 0x800d, I2C_DIR_READ | I2C_CLOCK_H | I2C_SEND_L);
93+ local n = cpu_read_register(d, 0x6000, 0);
94+ n = n & (1 << I2C_READBIT);
95+ return n == 0;
96+}
97+
98+
99+function send_bit(d, v)
100+{
101+ cpu_write(d, 0x800d, I2C_DIR_WRITE | I2C_CLOCK_L | I2C_SEND_L);
102+ cpu_write(d, 0x800d, I2C_DIR_WRITE | I2C_CLOCK_L | v);
103+ cpu_write(d, 0x800d, I2C_DIR_WRITE | I2C_CLOCK_H | v);
104+}
105+
106+function i2c_address_set(d, address, rw)
107+{
108+ do{
109+ local a = address;
110+ i2c_start(d);
111+ for(local i = 0; i < 7; i++){
112+ send_bit(d, a & I2C_SEND_H);
113+ a = a << 1;
114+ }
115+ send_bit(d, rw);
116+ }while(i2c_ack_wait(d) != true);
117+}
118+
119+function eeprom_address_set(d, address)
120+{
121+ for(local i = 0; i < 8; i++){
122+ local n = I2C_SEND_L;
123+ if(address & 0x80){
124+ n = I2C_SEND_H;
125+ }
126+ send_bit(d, n);
127+ address = address << 1;
128+ }
129+ i2c_ack_wait(d);
130+}
--- /dev/null
+++ b/client/trunk/anago/fme.ad
@@ -0,0 +1,155 @@
1+board <- {
2+ mappernum = 69, vram_mirrorfind = false, ppu_ramfind = false,
3+ cpu_rom = {
4+ size_base = 1 * mega, size_max = 2 * mega,
5+ banksize = 0x2000
6+ }, cpu_ram = {
7+ size_base = 0x2000, size_max = 0x2000,
8+ banksize = 0x2000
9+ }, ppu_rom = {
10+ size_base = 1 * mega, size_max = 2 *mega,
11+ banksize = 0x0400
12+ }
13+};
14+
15+/*
16+SUNSOFT-5A, SUNSOFT-5B, FME-7
17+[CPU writemap]
18+$6000-$7fff 7:0 RAM data (if RAM is enabled)
19+$8000-$9fff 3:0 memory register address
20+$a000-$bfff 7:0 memory register data
21+$c000-$dfff 3:0 audio register address
22+$e000-$ffff 7:0 audio register data
23+
24+[CPU readmap]
25+$6000-$7fff 7:0 Program ROM bank #0 or RAM
26+$8000-$9fff 7:0 Program ROM bank #1
27+$a000-$bfff 7:0 Program ROM bank #2
28+$c000-$dfff 7:0 Program ROM bank #3
29+$e000-$ffff 7:0 Program ROM bank #4 (fixed to bottom page)
30+
31+[PPU readmap] (PPU write map is undefined)
32+0x0000-0x03ff Charcter ROM bank #0|0x1000-0x13ff Charcter ROM bank #4
33+0x0400-0x07ff Charcter ROM bank #1|0x1400-0x17ff Charcter ROM bank #5
34+0x0800-0x0bff Charcter ROM bank #2|0x1800-0x1bff Charcter ROM bank #6
35+0x0c00-0x0fff Charcter ROM bank #3|0x1c00-0x1fff Charcter ROM bank #7
36+
37+[FME-7 memory register]
38+adr bit assignments
39+-------------------------
40+0-7 7:0 Charcter ROM bank #0 to #7
41+8 7 RAM enable bit 0:disable 1:enable
42+ 6 memory select at $6000-$7fff 0:ROM 1:RAM
43+ 4:0 CPU ROM page for bank #0
44+9-b 4:0 CPU ROM page for bank #1 to #3
45+c 1:0 PPU area VRAM control
46+d 7 φ2 counter decrement 0:disable 1:enable
47+ 0 φ2 counter overflow IRQ 0:disable 1:enable
48+e 7:0 φ2 counter value bit7:0
49+f 7:0 φ2 counter value bit15:8
50+
51+address 8, bit7:6 behave on FME-7
52+00 enabled ROM
53+01 disabled ROM and RAM
54+10 disabled ROM and RAM
55+11 enabled RAM
56+
57+audio register
58+(not analysed yet)
59+
60+*/
61+function sunsoft5_write(d, register_address, data)
62+{
63+ cpu_write(d, 0x8000, register_address);
64+ cpu_write(d, 0xa000, data);
65+}
66+
67+function cpu_dump(d, pagesize, banksize)
68+{
69+/*
70+ //dump ROM data via $6000-$7fff
71+ for(local i = 0; i < pagesize; i++){
72+ sunsoft5_write(d, 8, i);
73+ cpu_read(d, 0x6000, banksize);
74+ }
75+*/
76+ for(local i = 0; i < pagesize - 1; i++){
77+ sunsoft5_write(d, 9, i);
78+ cpu_read(d, 0x8000, banksize);
79+ }
80+ cpu_read(d, 0xe000, banksize);
81+}
82+
83+function ppu_dump(d, pagesize, banksize)
84+{
85+ local mul = 8;
86+ for(local i = 0; i < pagesize; i+= mul){
87+ for(local j = 0; j < mul; j++){
88+ sunsoft5_write(d, j, i + j);
89+ }
90+ ppu_read(d, 0, banksize * mul);
91+ }
92+}
93+
94+function cpu_ram_access(d, pagesize, banksize)
95+{
96+ sunsoft5_write(d, 8, 0xc0);
97+ cpu_ramrw(d, 0x6000, banksize);
98+ cpu_write(d, 0xa000, 0x00);
99+}
100+
101+/*
102+CPU memory bank
103+cpu address|rom address |page|task
104+$8000-$9fff|0x02000-0x03fff|1 |write 0x2aaa
105+$a000-$bfff|0x04000-0x05fff|2 |write 0x5555
106+$c000-$dfff|n * 0x2000 |n |program area
107+$e000-$ffff|0x3c000-0x3ffff|fix |program last page
108+
109+PPU memory bank
110+ppu address |rom address |page|task
111+0x0000-0x03ff|0x02800-0x02fff|0x0a|write 0x2aaa
112+0x0400-0x07ff|0x05000-0x057ff|0x14|write 0x5555
113+0x0800-0x0fff|未使用
114+0x1000-0x1fff|n * 0x1000 |n |program area
115+*/
116+function program_initalize(d, cpu_banksize, ppu_banksize)
117+{
118+ sunsoft5_write(d, 8, 0x40); //disable W-RAM
119+
120+ cpu_command(d, 0x2aaa, 0xe000, cpu_banksize);
121+ cpu_command(d, 0x5555, 0xe000, cpu_banksize);
122+ sunsoft5_write(d, 0xa,1);
123+ sunsoft5_write(d, 0xb,2);
124+
125+ ppu_command(d, 0x2aaa, 0x1000, ppu_banksize);
126+ ppu_command(d, 0x5555, 0x1400, ppu_banksize);
127+ ppu_command(d, 0x0000, 0x1800, ppu_banksize);
128+ sunsoft5_write(d, 4, 0x0a);
129+ sunsoft5_write(d, 5, 0x15);
130+ sunsoft5_write(d, 6, 0);
131+}
132+
133+function cpu_transfer(d, start, end, cpu_banksize)
134+{
135+ for(local i = start; i < end - 1; i += 1){
136+ sunsoft5_write(d, 0xb, 3);
137+ cpu_program(d, 0x8000, cpu_banksize);
138+ }
139+ cpu_program(d, 0xe000, cpu_banksize);
140+}
141+
142+function ppu_transfer(d, start, end, ppu_banksize)
143+{
144+/* local mul = 1;
145+ for(local i = start; i < end; i += mul){
146+ for(local j = 0; j < mul; j++){
147+ sunsoft5_write(d, j, i + j);
148+ }
149+ ppu_program(d, 0x0000, ppu_banksize * mul);
150+ }*/
151+ for(local i = start; i < end; i += 1){
152+ sunsoft5_write(d, 4, i);
153+ ppu_program(d, 0x1000, ppu_banksize);
154+ }
155+}
--- /dev/null
+++ b/client/trunk/anago/mmc1.ai
@@ -0,0 +1,14 @@
1+//send 1bit serial 5 times
2+function mmc1_write(d, address, data)
3+{
4+ local ar = [];
5+ for(local i = 0; i < 5; i++){
6+ ar.append(data);
7+ data = data >> 1;
8+ }
9+ cpu_write(d, address, ar);
10+
11+/* for(local i = 0; i < 5; i++){
12+ cpu_write(d, address, data >> i);
13+ }*/
14+}
--- /dev/null
+++ b/client/trunk/anago/mmc1_skrom.ag
@@ -0,0 +1,106 @@
1+board <- {
2+ mappernum = 1, vram_mirrorfind = false, ppu_ramfind = true,
3+ cpu_rom = {
4+ size_base = 1 * mega, size_max = 2 * mega,
5+ banksize = 0x4000,
6+ },
7+ cpu_ram = {
8+ size_base = 0x2000, size_max = 0x2000,
9+ banksize = 0x2000
10+ },
11+ ppu_rom = {
12+ size_base = 1 * mega, size_max = 1 * mega,
13+ banksize = 0x1000,
14+ }
15+};
16+
17+dofile("mmc1.ai");
18+
19+function cpu_dump(d, pagesize, banksize)
20+{
21+ cpu_write(d, 0x8000, 0x80); //serial count reset
22+ mmc1_write(d, 0x8000, 0x0c); //CPU/PPU bank configuration
23+ for(local i = 0; i < pagesize - 1; i += 1){
24+ mmc1_write(d, 0xe000, i | 0x10);
25+ cpu_read(d, 0x8000, banksize);
26+ }
27+ cpu_read(d, 0xc000, banksize);
28+}
29+
30+function ppu_dump(d, pagesize, banksize)
31+{
32+ for(local i = 0; i < pagesize; i += 2){
33+ mmc1_write(d, 0xa000, i);
34+ mmc1_write(d, 0xc000, i | 1);
35+ ppu_read(d, 0, banksize * 2);
36+ }
37+}
38+
39+function cpu_ram_access(d, pagesize, banksize)
40+{
41+ mmc1_write(d, 0x8000, 1 << 3);
42+ mmc1_write(d, 0xe000, 0);
43+ mmc1_write(d, 0xa000, 0);
44+ cpu_ramrw(d, 0x6000, banksize);
45+ mmc1_write(d, 0xe000, 0xff);
46+}
47+
48+/*
49+MMC1 ROM 2M + (ROM 1M or RAM) board
50+CPU memory bank for SLROM, SKROM, SGROM, SNROM
51+cpu address|rom address |page|task
52+$8000-$bfff|n * 0x4000|even 0x00|write 0x2aaa + write area
53+$c000-$ffff|0x3c000-0x3ffff|fix |write 0x5555
54+---------------------------------
55+$8000-$bfff|0x00000-0x03fff|fix |write 0x2aaa
56+$c000-$ffff|n * 0x4000|odd 0x01|write 0x5555 + write area
57+
58+PPU memory bank for SLROM, SKROM
59+ppu area use command only mask A0-A10 device
60+ppu address|rom address |page|task
61+$0000-$0fff|0x00000 * n |n |write area + 0x2aa + 0x555
62+$0000-$1fff|0x01000 * n |n+1 |write area
63+*/
64+function program_initalize(d, cpu_banksize, ppu_banksize)
65+{
66+ cpu_write(d, 0x8000, 0x80);
67+ mmc1_write(d, 0xa000, 0x10); //SNROM + MMC1A disable W-RAM
68+ mmc1_write(d, 0x8000, 0x1c);
69+ mmc1_write(d, 0xe000, 0x10); //MMC1B disable W-RAM
70+ cpu_command(d, 0x0000, 0x8000, cpu_banksize);
71+ cpu_command(d, 0x2aaa, 0x8000, cpu_banksize);
72+ cpu_command(d, 0x5555, 0xc000, cpu_banksize);
73+
74+ ppu_command(d, 0x0000, 0, ppu_banksize);
75+ ppu_command(d, 0x02aa, 0, ppu_banksize);
76+ ppu_command(d, 0x0555, 0, ppu_banksize);
77+}
78+
79+function cpu_transfer(d, start, end, cpu_banksize)
80+{
81+ local i = 0;
82+ local wram = 1 << 4; //W-RAM disable flag
83+ for(i = start; i < end - 2; i += 2){
84+ mmc1_write(d, 0x8000, 0x1c);
85+ mmc1_write(d, 0xe000, i | 0 | wram);
86+ cpu_program(d, 0x8000, cpu_banksize);
87+
88+ mmc1_write(d, 0x8000, 0x18);
89+ mmc1_write(d, 0xe000, i | 1 | wram);
90+ cpu_program(d, 0xc000, cpu_banksize);
91+ }
92+ mmc1_write(d, 0x8000, 0x1c);
93+ mmc1_write(d, 0xe000, i | wram);
94+ cpu_program(d, 0x8000, cpu_banksize);
95+ cpu_program(d, 0xc000, cpu_banksize);
96+}
97+
98+function ppu_transfer(d, start, end, ppu_banksize)
99+{
100+ for(local i = start; i < end; i+=2){
101+ mmc1_write(d, 0xa000, i)
102+ mmc1_write(d, 0xc000, i | 1);
103+ ppu_program(d, 0x0000, ppu_banksize * 2);
104+ }
105+}
106+
--- /dev/null
+++ b/client/trunk/anago/mmc1_surom.ag
@@ -0,0 +1,113 @@
1+/*
2+SUROM:
3+Dragon Quest IV, Dragon Warrior III, Dragon Warrior IV, Ninjara Hoi!
4+SXROM:
5+Best Play Pro Yakyuu Special, Final Fantasy I & II
6+*/
7+board <- {
8+ mappernum = 1, vram_mirrorfind = false, ppu_ramfind = false,
9+ cpu_rom = {
10+ size_base = 4 * mega, size_max = 4 * mega,
11+ banksize = 0x4000,
12+ },
13+ cpu_ram = {
14+ size_base = 0x2000, size_max = 0x8000,
15+ banksize = 0x2000
16+ },
17+ ppu_rom = {
18+ size_base = 0, size_max = 0,
19+ banksize = 0x1000,
20+ }
21+};
22+
23+dofile("mmc1.ai");
24+
25+function cpu_dump(d, pagesize, banksize)
26+{
27+ cpu_write(d, 0x8000, 0x80); //serial count reset
28+ mmc1_write(d, 0x8000, 0x0c); //CPU/PPU bank configuration
29+ for(local i = 0; i < pagesize; i += 0x10){
30+ mmc1_write(d, 0xa000, (i & 0x10) | 1);
31+ for(local j = 0; j < 0x10 - 1; j += 1){
32+ mmc1_write(d, 0xe000, j | 0x10);
33+ cpu_read(d, 0x8000, banksize);
34+ }
35+ cpu_read(d, 0xc000, banksize);
36+ }
37+}
38+
39+/*
40+http://nesdevwiki.org/wiki/SXROM
41+ CHR bank 0 (internal, $A000-$BFFF)
42+4bit0
43+-----
44+PSSxC
45+||| |
46+||| +- Select 4 KB CHR RAM bank at PPU $0000 (ignored in 8 KB mode)
47+|++--- Select 8 KB PRG RAM bank
48++----- Select 256 KB PRG ROM bank
49+*/
50+
51+function cpu_ram_access(d, pagesize, banksize)
52+{
53+ local sxrom_page = [0, 2 << 2, 1 << 2, 3 << 2];
54+ cpu_write(d, 0x8000, 0x80); //serial count reset
55+ mmc1_write(d, 0x8000, 1 << 3);
56+ mmc1_write(d, 0xe000, 0);
57+ for(local i = 0; i < pagesize; i += 1){
58+// mmc1_write(d, 0xa000, (i & 0x03) << 2);
59+ mmc1_write(d, 0xa000, sxrom_page[i]);
60+ cpu_ramrw(d, 0x6000, banksize);
61+ }
62+ mmc1_write(d, 0xe000, 0xff);
63+}
64+
65+/*
66+SUROM SXROM CPU memory bank
67+cpu address|rom address |page|task
68+--SNROM area -- even ----------------
69+$8000-$bfff|n * 0x4000|even 0x00|write 0x2aaa + write area
70+$c000-$ffff|0x3c000-0x3ffff|fix |write 0x5555
71+--SNROM area -- odd -----------------
72+$8000-$bfff|0x00000-0x03fff|fix |write 0x2aaa
73+$c000-$ffff|n * 0x4000|odd 0x01|write 0x5555 + write area
74+--SUROM area -- even ----------------
75+$8000-$bfff|n * 0x4000|even 0x20|write 0x2aaa + write area
76+$c000-$ffff|0x7c000-0x7ffff|fix |write 0x5555
77+--SUROM area -- odd -----------------
78+$8000-$bfff|0x40000-0x43fff|fix |write 0x2aaa
79+$c000-$ffff|n * 0x4000|odd 0x21|write 0x5555 + write area
80+*/
81+function program_initalize(d, cpu_banksize, ppu_banksize)
82+{
83+ cpu_write(d, 0x8000, 0x80);
84+ cpu_command(d, 0, 0x8000, cpu_banksize);
85+ cpu_command(d, 0x2aaa, 0x8000, cpu_banksize);
86+ cpu_command(d, 0x5555, 0xc000, cpu_banksize);
87+ mmc1_write(d, 0x8000, 0x0c);
88+ mmc1_write(d, 0xe000, 0x10); //cpubank #0
89+ mmc1_write(d, 0xa000, 0); //ROM area 1st 2M
90+}
91+
92+function cpu_transfer(d, start, end, cpu_banksize)
93+{
94+ local wram = 1 << 4; //W-RAM disable flag
95+ for(local k = 0; k < 0x20; k += 0x10){
96+ mmc1_write(d, 0xa000, k);
97+ for(local i = 0; i < 0x10; i += 2){
98+ //even page
99+ mmc1_write(d, 0x8000, 0x0c);
100+ mmc1_write(d, 0xe000, i | 0 | wram);
101+ cpu_program(d, 0x8000, cpu_banksize);
102+
103+ //odd page
104+ mmc1_write(d, 0x8000, 0x08);
105+ mmc1_write(d, 0xe000, i | 1 | wram);
106+ cpu_program(d, 0xc000, cpu_banksize);
107+ }
108+ }
109+}
110+
111+function ppu_transfer(d, start, end, bank)
112+{
113+}
--- /dev/null
+++ b/client/trunk/anago/mmc3_tkrom.ag
@@ -0,0 +1,120 @@
1+board <- {
2+ mappernum = 4, vram_mirrorfind = false, ppu_ramfind = true,
3+ cpu_rom = {
4+ size_base = 1 * mega, size_max = 4 * mega,
5+ banksize = 0x2000,
6+ },
7+ cpu_ram = {
8+ size_base = 0x2000, size_max = 0x2000,
9+ banksize = 0x2000,
10+ },
11+ ppu_rom = {
12+ size_base = 1 * mega, size_max = 2 * mega,
13+ banksize = 0x0400
14+ }
15+};
16+
17+function cpu_dump(d, pagesize, banksize)
18+{
19+ cpu_write(d, 0xa001, 0); //disable W-RAM
20+ for(local i = 0; i < pagesize - 2; i += 2){
21+ cpu_write(d, 0x8000, 6);
22+ cpu_write(d, 0x8001, i);
23+ cpu_write(d, 0x8000, 7);
24+ cpu_write(d, 0x8001, i | 1);
25+ cpu_read(d, 0x8000, banksize * 2);
26+ }
27+ cpu_read(d, 0xc000, banksize * 2);
28+}
29+function ppu_dump(d, pagesize, banksize)
30+{
31+ for(local i = 0; i < pagesize; i+=4){
32+ cpu_write(d, 0x8000, 2);
33+ cpu_write(d, 0x8001, i);
34+ cpu_write(d, 0x8000, 3);
35+ cpu_write(d, 0x8001, i | 1);
36+ cpu_write(d, 0x8000, 4);
37+ cpu_write(d, 0x8001, i | 2);
38+ cpu_write(d, 0x8000, 5);
39+ cpu_write(d, 0x8001, i | 3);
40+ ppu_read(d, 0x1000, banksize * 4);
41+ }
42+}
43+
44+/*
45+http://nesdevwiki.org/wiki/MMC3
46+ PRG RAM protect ($A001-$BFFF, odd)
47+7 bit 0
48+---- ----
49+RWxx xxxx
50+||
51+|+-------- Write protection (0: allow writes; 1: deny writes)
52++--------- Chip enable (0: disable chip; 1: enable chip)
53+*/
54+function cpu_ram_access(d, pagesize, banksize)
55+{
56+ cpu_write(d, 0xa001, 0x80);
57+ cpu_ramrw(d, 0x6000, banksize);
58+ cpu_write(d, 0xa001, 0x40);
59+}
60+
61+/*
62+CPU memory bank for T*ROM
63+cpu address|rom address |page|task
64+$8000-$9fff|0x02000-0x03fff|1 |write 0x2aaa
65+$a000-$bfff|n * 0x2000 |n |write area
66+$c000-$ffff|0x7c000-0x7ffff|fix |write 0x5555, boot area
67+
68+PPU memory bank for TLROM TKROM TKSROM
69+ppu address|rom address |page|task
70+$0000-$07ff|0x02800-0x02fff|0x0a|write 0x2aaa
71+$0800-$0fff|0x05000-0x057ff|0x14|write 0x5555
72+$1000-$1fff|n * 0x1000 |n |write area
73+*/
74+function program_initalize(d, cpu_banksize, ppu_banksize)
75+{
76+ cpu_write(d, 0xa001, 0); //disable W-RAM
77+
78+ cpu_command(d, 0x0000, 0xa000, cpu_banksize);
79+ cpu_command(d, 0x2aaa, 0x8000, cpu_banksize);
80+ cpu_command(d, 0x5555, 0xc000, 0x4000);
81+ cpu_write(d, 0x8000, 7);
82+ cpu_write(d, 0x8001, 0);
83+ cpu_write(d, 0x8000, 6);
84+ cpu_write(d, 0x8001, 1);
85+
86+ ppu_command(d, 0x0000, 0x1000, ppu_banksize);
87+ ppu_command(d, 0x2aaa, 0x0000, 0x0800);
88+ ppu_command(d, 0x5555, 0x0800, 0x0800);
89+ cpu_write(d, 0x8000, 2);
90+ cpu_write(d, 0x8001, 0);
91+ cpu_write(d, 0x8000, 0);
92+ cpu_write(d, 0x8001, 0x0a);
93+ cpu_write(d, 0x8000, 1);
94+ cpu_write(d, 0x8001, 0x14);
95+}
96+
97+function cpu_transfer(d, start, end, cpu_banksize)
98+{
99+ for(local i = start; i < end - 2; i += 1){
100+ cpu_write(d, 0x8000, 7);
101+ cpu_write(d, 0x8001, i);
102+ cpu_program(d, 0xa000, cpu_banksize);
103+ }
104+ cpu_program(d, 0xc000, cpu_banksize * 2)
105+}
106+
107+function ppu_transfer(d, start, end, ppu_banksize)
108+{
109+ for(local i = start; i < end; i += 4){
110+ cpu_write(d, 0x8000, 2);
111+ cpu_write(d, 0x8001, i);
112+ cpu_write(d, 0x8000, 3);
113+ cpu_write(d, 0x8001, i | 1);
114+ cpu_write(d, 0x8000, 4);
115+ cpu_write(d, 0x8001, i | 2);
116+ cpu_write(d, 0x8000, 5);
117+ cpu_write(d, 0x8001, i | 3);
118+ ppu_program(d, 0x1000, ppu_banksize * 4);
119+ }
120+}
--- /dev/null
+++ b/client/trunk/anago/mmc4_fkrom.ad
@@ -0,0 +1,41 @@
1+board <- {
2+ mappernum = 10, vram_mirrorfind = false, ppu_ramfind = true,
3+ cpu_rom = {
4+ size_base = 1 * mega, size_max = 2 * mega,
5+ banksize = 0x4000,
6+ },
7+ cpu_ram = {
8+ size_base = 0x2000, size_max = 0x2000,
9+ banksize = 0x2000,
10+ },
11+ ppu_rom = {
12+ size_base = 0x10000, size_max = 1 * mega,
13+ banksize = 0x1000
14+ }
15+};
16+
17+function cpu_dump(d, pagesize, banksize)
18+{
19+ for(local i = 0; i < pagesize - 1; i += 1){
20+ cpu_write(d, 0xa000, i);
21+ cpu_read(d, 0x8000, banksize);
22+ }
23+ cpu_read(d, 0xc000, banksize);
24+}
25+
26+function ppu_dump(d, pagesize, banksize)
27+{
28+ for(local i = 0; i < pagesize; i += 2){
29+ ppu_read(d, 0x0fd0, 0);
30+ cpu_write(d, 0xb000, i);
31+ ppu_read(d, 0x0fe0, 0);
32+ cpu_write(d, 0xc000, i);
33+
34+ ppu_read(d, 0x1fd0, 0);
35+ cpu_write(d, 0xd000, i + 1);
36+ ppu_read(d, 0x1fe0, 0);
37+ cpu_write(d, 0xe000, i + 1);
38+
39+ ppu_read(d, 0, banksize * 2);
40+ }
41+}
--- /dev/null
+++ b/client/trunk/anago/mmc5_ewrom.af
@@ -0,0 +1,155 @@
1+board <- {
2+ mappernum = 5,
3+ cpu_rom = {
4+ size_base = 2 * mega, size_max = 8 * mega,
5+ banksize = 0x2000
6+ },
7+ cpu_ram = {
8+ size_base = 0x2000, size_max = 0x8000,
9+ banksize = 0x2000
10+ },
11+ ppu_rom = {
12+ size_base = 2 * mega, size_max = 8 * mega,
13+ banksize = 0x0800
14+ },
15+ ppu_ramfind = true, vram_mirrorfind = false
16+};
17+
18+function cpu_dump(d, pagesize, banksize)
19+{
20+ local i;
21+ cpu_write(d, 0x5100, 0);
22+ for(i = 0x80; i < (pagesize | 0x80) - 2; i += 2){
23+ cpu_write(d, 0x5114, i);
24+ cpu_write(d, 0x5115, i | 1);
25+ cpu_read(d, 0x8000, banksize * 2);
26+ }
27+ cpu_write(d, 0x5116, i);
28+ cpu_write(d, 0x5117, 0xff);
29+ cpu_read(d, 0xc000, banksize * 2);
30+}
31+function ppu_dump(d, pagesize, banksize)
32+{
33+ local i;
34+ cpu_write(d, 0x5101, 2);
35+ cpu_write(d, 0x5130, 0);
36+ for(i = 0; (i < pagesize) && (i < 0x100); i += 4){
37+ cpu_write(d, 0x5121, i);
38+ cpu_write(d, 0x5123, i | 1);
39+ cpu_write(d, 0x5125, i | 2);
40+ cpu_write(d, 0x5127, i | 3);
41+ ppu_read(d, 0x0000, banksize * 4);
42+ }
43+ cpu_write(d, 0x5130, 0x03);
44+ for(; i < pagesize; i += 4){
45+ local j = i & ff;
46+ cpu_write(d, 0x5121, j);
47+ cpu_write(d, 0x5123, j | 1);
48+ cpu_write(d, 0x5125, j | 2);
49+ cpu_write(d, 0x5127, j | 3);
50+ ppu_read(d, 0x0000, banksize * 4);
51+ }
52+}
53+
54+/*
55+CPU memory bank
56+use 4bank mode ($6000- を除く)
57+cpu address|rom address |page|task
58+$8000-$9fff|n * 0x2000 |n |write area
59+$a000-$bfff|0x02000-0x03fff|1 |write (0x2aaa & 0x1fff) + 0x8000
60+$c000-$dfff|0x04000-0x05fff|2 |write (0x5555 & 0x1fff) + 0xa000
61+$e000-$efff|未使用 |----|未使用
62+コマンド用アドレス は RAM mode にしないと書き込みを受け付けない.
63+$c000 を書き込みエリアにすると ($c1xx & $7fff) = $51xx のバンクレジス
64+タが反応するらしい。よって $c000- はコマンドアドレスの使用に抑える。
65+
66+PPU memory bank
67+use 4bank mode (MAX 4M)
68+ppu address|rom address |page|task
69+$0000-$07ff|0x02800-0x02bff|0x0a|write (0x2aaa & 0x07ff) + 0
70+$0800-$0fff|0x05400-0x057ff|0x15|write (0x5555 & 0x07ff) + 0x800
71+$1000-$1fff|n * 0x0800 |n |write area
72+直接は関係ないが、PPU bank 数によってアクセスできる Charcter Memory の最値が異なる。
73+8つ. 2M, $5101 == 3
74+4つ. 4M, $5101 == 2
75+2つ. 8M, $5101 == 1
76+1つ. 16M, $5101 == 0
77+*/
78+function program_initalize(d, cpu_banksize, ppu_banksize)
79+{
80+ cpu_command(d, 0x0000, 0x8000, cpu_banksize);
81+ cpu_command(d, 0x2aaa, 0xa000, cpu_banksize);
82+ cpu_command(d, 0x5555, 0xc000, 0x4000);
83+ cpu_write(d, 0x5100, 3);
84+ cpu_write(d, 0x5113, 0);
85+ cpu_write(d, 0x5114, 0x80);
86+ cpu_write(d, 0x5115, 0x81);
87+ cpu_write(d, 0x5116, 0x82);
88+
89+ ppu_command(d, 0x0000, 0x1000, ppu_banksize);
90+ ppu_command(d, 0x2aaa, 0x0000, ppu_banksize);
91+ ppu_command(d, 0x5555, 0x0800, ppu_banksize);
92+ cpu_write(d, 0x5101, 2);
93+ cpu_write(d, 0x5121, 5);
94+ cpu_write(d, 0x5123, 0xa);
95+ cpu_write(d, 0x5125, 0);
96+
97+ cpu_write(d, 0x5104, 3);
98+ cpu_write(d, 0x5105, 0);
99+}
100+function cpu_transfer(d, start, end, cpu_banksize)
101+{
102+ for(local i = start; i < end - 1; i += 1){
103+ cpu_write(d, 0x5114, 0x80 | i);
104+ cpu_program(d, 0x8000, cpu_banksize);
105+ }
106+ //$e000- は書き込みが安定しないので末尾 page として $7f を指定する。
107+ cpu_write(d, 0x5114, 0x80 | 0x7f);
108+ cpu_program(d, 0x8000, cpu_banksize);
109+}
110+/*
111+using upper charcter memory address register (0x5130)
112+this method can program A14-A0 device*/
113+function ppu_transfer(d, start, end, banksize)
114+{
115+ local i;
116+ cpu_write(d, 0x5130, 0);
117+ for(i = start; (i < end) && (i < 0x100); i += 2){
118+ cpu_write(d, 0x5125, i);
119+ cpu_write(d, 0x5127, i | 1);
120+ ppu_program(d, 0x1000, banksize * 2);
121+ }
122+ cpu_write(d, 0x5130, 0x03);
123+ for(; i < end; i += 2){
124+ cpu_write(d, 0x5125, (i & 0xff));
125+ cpu_write(d, 0x5127, (i & 0xff) | 1);
126+ ppu_program(d, 0x1000, banksize * 2);
127+ }
128+}
129+/*
130+changing charcter bank size method which is tricky.
131+this method can program A10-A0 device only
132+memory bank configuration for 0x80000-0xfffff
133+ppu address|rom address |page|task
134+$0000-$0fff|0x80000-0x80fff|0x00|write 0x02aa, 0x0555
135+$1000-$1fff|n * 0x1000 |n |write area
136+*/
137+/*
138+function ppu_transfer(d, start, end, ppu_banksize)
139+{
140+ local i;
141+ for(i = start; (i < end) && (i < 0x100); i += 2){
142+ cpu_write(d, 0x5125, i);
143+ cpu_write(d, 0x5127, i | 1);
144+ ppu_program(d, 0x1000, ppu_banksize * 2);
145+ }
146+ ppu_banksize *= 2;
147+ cpu_write(d, 0x5101, 1);
148+ ppu_command(d, 0x02aa, 0x0000, ppu_banksize);
149+ ppu_command(d, 0x0555, 0x0000, ppu_banksize);
150+ cpu_write(d, 0x5123, 0);
151+ for(i; i < end; i += 2){
152+ cpu_write(d, 0x5127, i >> 1);
153+ ppu_program(d, 0x1000, ppu_banksize);
154+ }
155+}*/
--- /dev/null
+++ b/client/trunk/anago/namcot_163.ag
@@ -0,0 +1,46 @@
1+/*
2+Namcot 129/163
3+
4+No battery, no external RAM:
5+ Star Wars (129), Namco Classic, Youkai Douchuki, Final Lap,
6+ Erika to Satoru no Yumebouken, Rolling Thunder, Dragon Ninja,
7+ Mappy Kids, Namco Classic II
8+
9+Battery-backuped Memory is used by an external RAM:
10+ Sangokushi, King of Kings, Juvei Quest,
11+ Megami Tensei II, Sangokushi II (uses IRQ)
12+
13+Battery-backuped Memory is used by an internal RAM:
14+ Dokuganryu Masamune, Kaiju Monogatari, Mindseeker, Hydride3,
15+ Famista '90, Battle Fleet
16+*/
17+board <- {
18+ mappernum = 19,
19+ cpu_rom = {
20+ size_base = 2 * mega, size_max = 4 * mega,
21+ banksize = 0x2000
22+ },
23+ cpu_ram = {
24+ size_base = 0x0080, size_max = 0x2000,
25+ banksize = 0x2000
26+ },
27+ ppu_rom = {
28+ size_base = 2 * mega, size_max = 2 * mega,
29+ banksize = 0x0400
30+ },
31+ ppu_ramfind = false,
32+ vram_mirrorfind = false
33+};
34+dofile("namcot_19.ai");
35+
36+function cpu_ram_access(d, pagesize, banksize)
37+{
38+ if(pagesize == 0){ //internal RAM
39+ cpu_write(d, 0xf800, 0x80); //autoinrement on
40+ cpu_ramrw(d, 0x4800, 0x80);
41+ }else{ //external RAM
42+ cpu_write(d, 0xf800, 0x40);
43+ cpu_ramrw(d, 0x6000, banksize);
44+ cpu_write(d, 0xf800, 0x4f);
45+ }
46+}
--- /dev/null
+++ b/client/trunk/anago/namcot_175.ae
@@ -0,0 +1,34 @@
1+/*
2+Namcot 175
3+
4+Wagan Land 2, Famista'91, Family Circuit '91, Chibimaruko chan,
5+Heisei Tensai Bakabon
6+
7+Family Circuit '91 has Program ROM(4M), Charcter ROM and external
8+Battery Backuped WorkRAM.
9+*/
10+board <- {
11+ mappernum = 19, //210,
12+ cpu_rom = {
13+ size_base = 2 * mega, size_max = 4 * mega,
14+ banksize = 0x2000
15+ },
16+ cpu_ram = {
17+ size_base = 0x0800, size_max = 0x0800,
18+ banksize = 0x2000
19+ },
20+ ppu_rom = {
21+ size_base = 2 * mega, size_max = 2 * mega,
22+ banksize = 0x0400
23+ },
24+ ppu_ramfind = false,
25+ vram_mirrorfind = true
26+};
27+dofile("namcot_19.ai");
28+
29+function cpu_ram_access(d, pagesize, banksize)
30+{
31+ cpu_write(d, 0xc000, 0x01);
32+ cpu_ramrw(d, 0x6000, 0x0800);
33+ cpu_write(d, 0xc000, 0x00);
34+}
--- /dev/null
+++ b/client/trunk/anago/namcot_19.ai
@@ -0,0 +1,76 @@
1+/*
2+iNES mapper #19
3+
4+Many cartridges uses epoxies for ROM, RAM and mapper. Few cartridges
5+uses discrete parts. Other functions are various though the memory
6+mapping is common.
7+
8+The mistake of an old document is an etymology of 'namcot 106'. I have
9+seen mapper IC with 163 (well known chip), 129, 175 and 340 for #19.
10+I have never seen labeled IC with '106'.
11+'106' is informal virtual name, and the relic of old emulators.
12+*/
13+function cpu_dump(d, pagesize, banksize)
14+{
15+ for(local i = 0; i < pagesize - 2; i += 2){
16+ cpu_write(d, 0xe000, i);
17+ cpu_write(d, 0xe800, i | 1);
18+ cpu_read(d, 0x8000, banksize * 2);
19+ }
20+ cpu_write(d, 0xf000, 0x3e);
21+ cpu_read(d, 0xc000, banksize * 2);
22+}
23+
24+function ppu_dump(d, pagesize, banksize)
25+{
26+ cpu_write(d, 0xe800, 0xe0);
27+ for(local i = 0; i < pagesize; i += 8){
28+ local address = 0x8000;
29+ for(local j = 0; j < 8; j++){
30+ cpu_write(d, address, i | j);
31+ address += 0x0800;
32+ }
33+ ppu_read(d, 0, banksize * 8);
34+ }
35+}
36+
37+function program_initalize(d, cpu_banksize, ppu_banksize)
38+{
39+ cpu_command(d, 0x0000, 0xa000, cpu_banksize);
40+ cpu_command(d, 0x2aaa, 0x8000, cpu_banksize);
41+ cpu_command(d, 0x5555, 0xa000, cpu_banksize);
42+ cpu_write(d, 0xe000, 0x41);
43+ cpu_write(d, 0xe800, 0xe2);
44+
45+ ppu_command(d, 0x0000, 0x0000, ppu_banksize);
46+ ppu_command(d, 0x2aaa, 0x0400, ppu_banksize);
47+ ppu_command(d, 0x5555, 0x0800, ppu_banksize);
48+ cpu_write(d, 0x8000, 0x00);
49+ cpu_write(d, 0x8800, 0x0a);
50+ cpu_write(d, 0x9000, 0x15);
51+ //map 0x2000-0x2fff is RAM
52+ cpu_write(d, 0xc000, 0xe0);
53+ cpu_write(d, 0xc800, 0xe0);
54+ cpu_write(d, 0xd000, 0xe1);
55+ cpu_write(d, 0xd800, 0xe1);
56+}
57+
58+function cpu_transfer(d, start, end, cpu_banksize)
59+{
60+ for(local i = start; i < end - 1; i += 1){
61+ cpu_write(d, 0xf000, i | 0xe0);
62+ cpu_program(d, 0xc000, cpu_banksize);
63+ }
64+ cpu_program(d, 0xe000, cpu_banksize)
65+}
66+
67+function ppu_transfer(d, start, end, ppu_banksize)
68+{
69+ for(local i = start; i < end; i += 4){
70+ cpu_write(d, 0xa000, i);
71+ cpu_write(d, 0xa800, i | 1);
72+ cpu_write(d, 0xb000, i | 2);
73+ cpu_write(d, 0xb800, i | 3);
74+ ppu_program(d, 0x1000, ppu_banksize * 4);
75+ }
76+}
--- /dev/null
+++ b/client/trunk/anago/namcot_340.ad
@@ -0,0 +1,24 @@
1+/*
2+Namcot 340
3+
4+Splatter House, Top Striker, Famista '92, Dream Master,
5+Wagan Land3, Famista '93, Famista '94
6+*/
7+board <- {
8+ mappernum = 19, //210,
9+ cpu_rom = {
10+ size_base = 2 * mega, size_max = 4 * mega,
11+ banksize = 0x2000
12+ },
13+ cpu_rom = {
14+ size_base = 0x0800, size_max = 0x0800,
15+ banksize = 0x2000
16+ },
17+ ppu_rom = {
18+ size_base = 2 * mega, size_max = 2 * mega,
19+ banksize = 0x0400
20+ },
21+ ppu_ramfind = false,
22+ vram_mirrorfind = false
23+};
24+dofile("namcot_19.ai");
--- /dev/null
+++ b/client/trunk/anago/nrom.ad
@@ -0,0 +1,21 @@
1+board <- {
2+ mappernum = 0,
3+ cpu_rom = {
4+ size_base = 0x8000, size_max = 0x8000
5+ banksize = 0x8000
6+ },
7+ ppu_rom= {
8+ size_base = 0x8000, size_max = 0x2000,
9+ banksize = 0x2000
10+ },
11+ ppu_ramfind = false, vram_mirrorfind = true
12+};
13+function cpu_dump(d, pagesize, banksize)
14+{
15+ cpu_read(d, 0x8000, 0x4000);
16+ cpu_read(d, 0xc000, 0x4000);
17+}
18+function ppu_dump(d, pagesize, banksize)
19+{
20+ ppu_read(d, 0, banksize);
21+}
--- /dev/null
+++ b/client/trunk/anago/sunsoft-4.ae
@@ -0,0 +1,63 @@
1+board <- {
2+ mappernum = 68, ppu_ramfind = false, vram_mirrorfind = false,
3+ cpu_rom = {
4+ size_base = 1 * mega, size_max = 2 * mega,
5+ banksize = 0x4000
6+ },
7+ cpu_ram = {
8+ size_base = 0x2000, size_max = 0x2000, banksize = 0x2000
9+ },
10+ ppu_rom = {
11+ size_base = 1 * mega, size_max = 2 * mega,
12+ banksize = 0x0800
13+ }
14+};
15+
16+function cpu_dump(d, pagesize, banksize)
17+{
18+ for(local i = 0; i < pagesize - 1; i += 1){
19+ cpu_write(d, 0xf000, i);
20+ cpu_read(d, 0x8000, banksize);
21+ }
22+ cpu_read(d, 0xc000, banksize);
23+}
24+
25+/*
26+After Burner CRC32 list
27+0x88f202f0 Program ROM
28+0x10935d10 Charcter ROM #0
29+0x0bc56f7a Charcter ROM #1
30+0xa75cb06d Charcter ROM #0+#1
31+0xf2ce3641 total
32+*/
33+function ppu_dump(d, pagesize, banksize)
34+{
35+ //dump uses 0x0000-0x1fff
36+/* for(local i = 0; i < pagesize; i += 4){
37+ cpu_write(d, 0x8000, i);
38+ cpu_write(d, 0x9000, i | 1);
39+ cpu_write(d, 0xa000, i | 2);
40+ cpu_write(d, 0xb000, i | 3);
41+ ppu_read(d, 0, banksize * 4);
42+ }
43+ //dump uses 0x2000-0x27ff*/
44+/* cpu_write(d, 0xe000, 0x10);
45+ for(local i = 0; i < pagesize*2; i += 2){
46+ cpu_write(d, 0xc000, i);
47+ cpu_write(d, 0xd000, i | 1);
48+ ppu_read(d, 0x2000, banksize);
49+ }*/
50+ //dump uses 0x2000-0x23ff*/
51+ cpu_write(d, 0xe000, 0x13);
52+ for(local i = 0; i < pagesize*2; i += 1){
53+ cpu_write(d, 0xd000, i);
54+ ppu_read(d, 0x2000, 0x400);
55+ }
56+}
57+
58+function cpu_ram_access(d, pagesize, banksize)
59+{
60+ cpu_write(d, 0xf000, 0x10);
61+ cpu_ramrw(d, 0x6000, banksize);
62+ cpu_write(d, 0xf000, 0);
63+}
--- /dev/null
+++ b/client/trunk/anago/sunsoft-4.ag
@@ -0,0 +1,131 @@
1+board <- {
2+ mappernum = 68, ppu_ramfind = false, vram_mirrorfind = false,
3+ cpu_rom = {
4+ size_base = 1 * mega, size_max = 2 * mega,
5+ banksize = 0x4000
6+ },
7+ cpu_ram = {
8+ size_base = 0x2000, size_max = 0x2000, banksize = 0x2000
9+ },
10+ ppu_rom = {
11+ size_base = 1 * mega, size_max = 2 * mega,
12+ banksize = 0x0800
13+ }
14+};
15+
16+/*
17+SUNSOFT-4 manages, banksize:0x4000, pagesize:0x10
18+[Nantetatte Baseball]
19+page 0 to 7:
20+uses subcartridge + SUNSOFT-6 controller
21+page 8 to F:
22+main PCB ROM data, data size is 0x20000
23+
24+[other games]
25+ROM size is 0x20000, page 0 to 7 and page 8 to f are same data (mirrored).
26+*/
27+function cpu_dump(d, pagesize, banksize)
28+{
29+ local i;
30+ if(pagesize == 8){
31+ i = 8;
32+ pagesize += 8;
33+ }else{
34+ i = 0;
35+ }
36+ //page 0 to 7 uses via Nanntettate! Baseball Subcartridge
37+ for(; i < 8; i += 1){
38+ cpu_write(d, 0xf000, i); //set page and enable SUNSOFT-6 (disable Workram)
39+ cpu_write(d, 0x6000, 0); //active ROM
40+ cpu_read(d, 0x8000, banksize);
41+ }
42+ //page 8 to 0xe uses normal ROM
43+ for(; i < pagesize - 1; i += 1){
44+ cpu_write(d, 0xf000, i);
45+ cpu_read(d, 0x8000, banksize);
46+ }
47+ cpu_read(d, 0xc000, banksize);
48+}
49+
50+/*
51+SUNSOFT-4 can map Charcter ROM to nametable area.
52+
53+Charcter data (0x0000 to 0x1fff) banksize is 0x0800
54+Nametable data (0x2000 to 0x2fff) banksize is 0x0400
55+
56+Charcter data
57+A[17:11] = reg[6:0]
58+A[10:0] = PPU A[10:0]
59+
60+Nametable data
61+A[17] = 1
62+A[16:10] = reg[6:0]
63+A[9:0] = PPU A[9:0]
64+
65+After Burner CRC32 list
66+0x88f202f0 Program ROM
67+0x10935d10 Charcter ROM #0
68+0x0bc56f7a Charcter ROM #1
69+0xa75cb06d Charcter ROM #0+#1
70+0xf2ce3641 total
71+*/
72+function ppu_dump(d, pagesize, banksize)
73+{
74+ for(local i = 0; i < pagesize; i += 4){
75+ cpu_write(d, 0x8000, i);
76+ cpu_write(d, 0x9000, i | 1);
77+ cpu_write(d, 0xa000, i | 2);
78+ cpu_write(d, 0xb000, i | 3);
79+ ppu_read(d, 0, banksize * 4);
80+ }
81+}
82+
83+function cpu_ram_access(d, pagesize, banksize)
84+{
85+ cpu_write(d, 0xf000, 0x10); //enable Workram, disable SUNSOFT-6
86+ cpu_ramrw(d, 0x6000, banksize);
87+ cpu_write(d, 0xf000, 0);
88+}
89+
90+/*
91+SUNSOFT-4 has single switchable CPU bank. flash memory program address bit can uses A10:0 type.
92+[CPU]
93+$8000-$ffff -> programming area
94+
95+[PPU]
96+0x0000-0x07ff -> 0x02800-0x02fff, uses 0x2aaa
97+0x0800-0x0fff -> 0x05000-0x05800, uses 0x5555
98+0x1000-0x17ff -> ID area (reserved)
99+0x1800-0x1fff -> programming area
100+*/
101+function program_initalize(d, cpu_banksize, ppu_banksize)
102+{
103+ cpu_command(d, 0x0000, 0x8000, cpu_banksize);
104+ cpu_command(d, 0x2aaa, 0x8000, cpu_banksize);
105+ cpu_command(d, 0x5555, 0xc000, cpu_banksize);
106+ cpu_write(d, 0xf000, 0); //disable Workram
107+
108+ ppu_command(d, 0x2aaa, 0x0000, ppu_banksize);
109+ cpu_write(d, 0x8000, 0x05);
110+ ppu_command(d, 0x5555, 0x0800, ppu_banksize);
111+ cpu_write(d, 0x9000, 0x0a);
112+ ppu_command(d, 0x0000, 0x1000, ppu_banksize);
113+ cpu_write(d, 0xa000, 0);
114+}
115+
116+function cpu_transfer(d, start, end, banksize)
117+{
118+ for(local i = start; i < end - 1; i += 1){
119+ cpu_write(d, 0xf000, i);
120+ cpu_program(d, 0x8000, banksize);
121+ }
122+ cpu_program(d, 0xc000, banksize)
123+}
124+
125+function ppu_transfer(d, start, end, banksize)
126+{
127+ for(local i = start; i < end; i += 1){
128+ cpu_write(d, 0xb000, i);
129+ ppu_program(d, 0x1800, banksize);
130+ }
131+}
--- /dev/null
+++ b/client/trunk/anago/sunsoft-4s.ad
@@ -0,0 +1,23 @@
1+board <- {
2+ mappernum = 68, ppu_ramfind = false, vram_mirrorfind = false,
3+ cpu_rom = {
4+ size_base = 0x4000, size_max = 2 * mega,
5+ banksize = 0x4000
6+ },
7+ cpu_ram = {
8+ size_base = 0x2000, size_max = 0x2000, banksize = 0x2000
9+ },
10+ ppu_rom = {
11+ size_base = 0, size_max = 0,
12+ banksize = 0x0800
13+ }
14+};
15+
16+function cpu_dump(d, pagesize, banksize)
17+{
18+ cpu_write(d, 0xf000, 7);
19+ cpu_write(d, 0x6000, 0x0d);
20+// cpu_write(d, 0x6000, 0xb0);
21+ cpu_read(d, 0x8000, 0x2000);
22+ cpu_read(d, 0xa000, 0x2000);
23+}
--- /dev/null
+++ b/client/trunk/anago/taito_x1_005.ae
@@ -0,0 +1,57 @@
1+/*
2+Taito X1-005
3+TFC-FM-5900 不動明王伝のみ Program ROM size は 2M
4+
5+Minelvaton Saga
6+$7f00-$7f7f save RAM area
7+$7f80-$7fff save RAM area, mirror
8+*/
9+board <- {
10+ mappernum = 80, ppu_ramfind = false, vram_mirrorfind = false,
11+ cpu_rom = {
12+ size_base = 1 * mega, size_max = 2 * mega,
13+ banksize = 0x2000
14+ },
15+ cpu_ram = {
16+ size_base = 0x100 * 0x20, size_max = 0x100 * 0x20,
17+ banksize = 0x2000
18+ }
19+ ppu_rom = {
20+ size_base = 1 * mega, size_max = 1 * mega,
21+ banksize = 0x2000 / 8 //0x0800*2 + 0x0400 * 4
22+ }
23+};
24+
25+function cpu_dump(d, pagesize, banksize)
26+{
27+ local i;
28+ for(i = 0; i < pagesize - 2; i += 2){
29+ cpu_write(d, 0x7efa, i);
30+ cpu_write(d, 0x7efc, i | 1);
31+ cpu_read(d, 0x8000, banksize * 2);
32+ }
33+ cpu_write(d, 0x7efe, i);
34+ cpu_read(d, 0xc000, banksize * 2);
35+}
36+
37+function ppu_dump(d, pagesize, banksize)
38+{
39+ for(local i = 0; i < pagesize; i += 8){
40+ local ar = [i, i|2, i|4, i|5, i|6, i|7];
41+ cpu_write(d, 0x7ef0, ar);
42+ ppu_read(d, 0x0000, banksize * 8);
43+ }
44+}
45+
46+/*
47+0x2000 byte のデータの offset 0x1f00-0x1f7f のみ有効
48+*/
49+function cpu_ram_access(d, pagesize, banksize)
50+{
51+ cpu_write(d, 0x7ef8, 0xa3);
52+ for(local i = 0; i < 0x1f80; i += 0x80){
53+ cpu_ramrw(d, 0x7f00, 0x0080);
54+ }
55+ cpu_ramrw(d, 0x6000, 0x0080); //offset 0x1f80-0x1fff を捨てる
56+ cpu_write(d, 0x7ef8, 0x00);
57+}
--- /dev/null
+++ b/client/trunk/anago/unrom.af
@@ -0,0 +1,45 @@
1+board <- {
2+ mappernum = 2, vram_mirrorfind = true, ppu_ramfind = false,
3+ cpu_rom = {
4+ size_base = 1 * mega, size_max = 2 * mega,
5+ banksize = 0x4000
6+ },
7+ ppu_rom = {
8+ size_base = 0, size_max = 0,
9+ banksize = 0x2000
10+ }
11+};
12+
13+function cpu_dump(d, pagesize, banksize)
14+{
15+ for(local i = 0; i < pagesize - 1; i += 1){
16+ cpu_write(d, 0x8000, i);
17+ cpu_read(d, 0x8000, banksize);
18+ }
19+ cpu_read(d, 0xc000, banksize);
20+}
21+
22+/*
23+UNROM/UOROM programming notice
24+command address supports A10-A0 device. A14-A0 is not supported!
25+*/
26+function program_initalize(d, cpu_banksize, ppu_banksize)
27+{
28+ cpu_write(d, 0x8000, 0);
29+ cpu_command(d, 0, 0x8000, cpu_banksize);
30+ cpu_command(d, 0x02aa, 0xc000, cpu_banksize);
31+ cpu_command(d, 0x0555, 0xc000, cpu_banksize);
32+}
33+
34+function cpu_transfer(d, start, end, cpu_banksize)
35+{
36+ for(local i = start; i < end - 1; i += 1){
37+ cpu_write(d, 0xe000, i);
38+ cpu_program(d, 0x8000, cpu_banksize);
39+ }
40+ cpu_program(d, 0xc000, cpu_banksize);
41+}
42+
43+function ppu_transfer(d, start, end, ppu_banksize)
44+{
45+}
--- /dev/null
+++ b/client/trunk/anago/vrc1.ad
@@ -0,0 +1,35 @@
1+//konami VRC(I)
2+board <- {
3+ mappernum = 75,
4+ cpu_rom = {
5+ size_base = 1 * mega, size_max = 1 * mega,
6+ banksize = 0x2000
7+ },
8+ ppu_rom= {
9+ size_base = 1 * mega, size_max = 1 * mega,
10+ banksize = 0x1000
11+ },
12+ ppu_ramfind = false, vram_mirrorfind = false
13+};
14+function cpu_dump(d, pagesize, banksize)
15+{
16+ local i;
17+ for(i = 0; i < pagesize - 2; i += 2){
18+ cpu_write(d, 0x8000, i);
19+ cpu_write(d, 0xa000, i | 1);
20+ cpu_read(d, 0x8000, banksize * 2);
21+ }
22+ cpu_write(d, 0xc000, i);
23+ cpu_read(d, 0xc000, banksize * 2);
24+}
25+function ppu_dump(d, pagesize, banksize)
26+{
27+ for(local i = 0; i < pagesize; i += 0x10){
28+ cpu_write(d, 0x9000, i == 0 ? 0 : (0x3 << 1));
29+ for(local j = 0; j < 0x10; j += 2){
30+ cpu_write(d, 0xe000, j);
31+ cpu_write(d, 0xf000, j | 1);
32+ ppu_read(d, 0, banksize * 2);
33+ }
34+ }
35+}
--- /dev/null
+++ b/client/trunk/anago/vrc2a.ad
@@ -0,0 +1,52 @@
1+/*
2+VRCII A0,A1 swap + charcter ROM address bus shiftx1
3+051744 jumper G?
4+VRC-CPU|databus
5+A0 - A1|A0: xxxx210x
6+A1 - A0|A1: xxxx6543
7+VRC-CHRCTER ROM
8+A11-A17 = A10-A16
9+*/
10+board <- {
11+ mappernum = 22, vram_mirrorfind = false, ppu_ramfind = false,
12+ cpu_rom = {
13+ size_base = 1 * mega, size_max = 1 * mega,
14+ banksize = 0x2000
15+ },
16+ ppu_rom = {
17+ size_base = 1 * mega, size_max = 1 * mega,
18+ banksize = 0x2000 / 8
19+ }
20+};
21+dofile("vrc4.ai");
22+function cpu_dump(d, pagesize, banksize)
23+{
24+ vrc4_cpu_dump(d, pagesize, banksize, 1, 0);
25+}
26+
27+
28+function vrc2a_ppubank_set(d, addr, i, j, r0, r1)
29+{
30+ local a1 = 1 << r0;
31+ local a2 = 1 << r1;
32+ local a3 = a1|a2;
33+
34+ cpu_write(d, addr | a1, i >> 3);
35+ cpu_write(d, addr, i << 1);
36+ cpu_write(d, addr | a3, j >> 3);
37+ cpu_write(d, addr | a2, j << 1);
38+}
39+
40+function ppu_dump(d, pagesize, banksize)
41+{
42+ local r0 = 1;
43+ local r1 = 0;
44+
45+ for(local i = 0; i < pagesize; i += 8){
46+ vrc2a_ppubank_set(d, 0xb000, i | 0, i | 1, r0, r1);
47+ vrc2a_ppubank_set(d, 0xc000, i | 2, i | 3, r0, r1);
48+ vrc2a_ppubank_set(d, 0xd000, i | 4, i | 5, r0, r1);
49+ vrc2a_ppubank_set(d, 0xe000, i | 6, i | 7, r0, r1);
50+ ppu_read(d, 0x0000, banksize * 8);
51+ }
52+}
--- /dev/null
+++ b/client/trunk/anago/vrc2b.ad
@@ -0,0 +1,26 @@
1+/*
2+VRC2B; R0=A0, R1=A1
3+じゃんン子チエ のみ d12 で dump すること。
4+*/
5+board <- {
6+ mappernum = 23,
7+ cpu_rom = {
8+ size_base = 1 * mega, size_max = 2 * mega,
9+ banksize = 0x2000
10+ },
11+ ppu_rom= {
12+ size_base = 1 * mega, size_max = 2 * mega,
13+ banksize = 0x2000 / 8
14+ },
15+ ppu_ramfind = false, vram_mirrorfind = false
16+};
17+dofile("vrc4.ai");
18+function cpu_dump(d, pagesize, banksize)
19+{
20+ vrc4_cpu_dump(d, pagesize, banksize, 0, 1);
21+}
22+
23+function ppu_dump(d, pagesize, banksize)
24+{
25+ vrc4_ppu_dump(d, pagesize, banksize, 0, 1);
26+}
--- /dev/null
+++ b/client/trunk/anago/vrc3.ad
@@ -0,0 +1,41 @@
1+/*
2+konami VRCIII
3+RC821
4+各レジスタは4bit
5+write
6+$8000 IRQ cpu clock count, bit0-3??
7+$9000 IRQ cpu clock count, bit4-7??
8+$a000 IRQ cpu clock count, bit8-11
9+$b000 IRQ cpu clock count, bit12-15
10+$c000 IRQ enable
11+$d000 IRQ Acknowledge
12+$f000 bit0-2 pagenumber at CPU address $8000-$bfff
13+ bit3 1: ROM address 0x1c000-0x1cfff map CPU address $c000-$cfff
14+ 0: IRQ status? at CPU address $c000-$cfff
15+read
16+$8000-$bfff 可変エリア, write $f000 bit0-2
17+$c000-$cfff 可変エリア, write $f000 bit3
18+$d000-$ffff 固定エリア, ROM address 0x1d000-0x1ffff
19+*/
20+
21+board <- {
22+ mappernum = 73,
23+ cpu_rom = {
24+ size_base = 1 * mega, size_max = 1 * mega,
25+ banksize = 0x4000
26+ },
27+ ppu_rom= {
28+ size_base = 0, size_max = 0,
29+ banksize = 0x2000
30+ },
31+ ppu_ramfind = false, vram_mirrorfind = true
32+};
33+function cpu_dump(d, pagesize, banksize)
34+{
35+ for(local i = 0; i < pagesize - 1; i += 1){
36+ cpu_write(d, 0xf000, i);
37+ cpu_read(d, 0x8000, banksize);
38+ }
39+ cpu_write(d, 0xf000, 1 << 3);
40+ cpu_read(d, 0xc000, banksize);
41+}
--- /dev/null
+++ b/client/trunk/anago/vrc4.ai
@@ -0,0 +1,70 @@
1+function vrc4_cpu_dump(d, pagesize, banksize, r0, r1)
2+{
3+ local a2 = 1 << r1;
4+ cpu_write(d, 0x9000 | a2, 0);
5+ for(local i = 0; i < pagesize - 2; i += 2){
6+ cpu_write(d, 0x8000, i);
7+ cpu_write(d, 0xa000, i | 1);
8+ cpu_read(d, 0x8000, banksize * 2);
9+ }
10+ cpu_write(d, 0x9000 | a2, 0x02);
11+ cpu_write(d, 0x8000, 0x1e);
12+ cpu_read(d, 0xc000, banksize * 2);
13+}
14+function ppu_bank_set(d, addr, i, j, r0, r1)
15+{
16+ local a1 = (1 << r0);
17+ local a2 = (1 << r1);
18+ local a3 = a1 | a2;
19+
20+ cpu_write(d, addr | a1, i >> 4);
21+ cpu_write(d, addr, i & 0xf);
22+ cpu_write(d, addr | a3, j >> 4);
23+ cpu_write(d, addr | a2, j & 0xf);
24+}
25+function vrc4_ppu_dump(d, pagesize, banksize, r0, r1)
26+{
27+ for(local i = 0; i < pagesize; i += 8){
28+ ppu_bank_set(d, 0xb000, i | 0, i | 1, r0, r1);
29+ ppu_bank_set(d, 0xc000, i | 2, i | 3, r0, r1);
30+ ppu_bank_set(d, 0xd000, i | 4, i | 5, r0, r1);
31+ ppu_bank_set(d, 0xe000, i | 6, i | 7, r0, r1);
32+ ppu_read(d, 0x0000, banksize * 8);
33+ }
34+}
35+
36+function vrc4_program_initialize(d, cpu_banksize, ppu_banksize, r0, r1)
37+{
38+ local a2 = 1 << r1;
39+ cpu_write(d, 0x9000 | a2, 0);
40+ cpu_write(d, 0x8000, 1);
41+ cpu_write(d, 0xa000, 0);
42+
43+ cpu_command(d, 0, 0xa000, cpu_banksize);
44+ cpu_command(d, 0x2aaa, 0x8000, cpu_banksize);
45+ cpu_command(d, 0x5555, 0xc000, cpu_banksize);
46+
47+ ppu_bank_set(d, 0xb000, 0x0a, 0x15, r0, r1);
48+ ppu_bank_set(d, 0xc000, 0x00, 0x00, r0, r1);
49+ ppu_command(d, 0, 0x0800, ppu_banksize);
50+ ppu_command(d, 0x2aaa, 0x0000, ppu_banksize);
51+ ppu_command(d, 0x5555, 0x0400, ppu_banksize);
52+}
53+
54+function cpu_transfer(d, start, end, cpu_banksize)
55+{
56+ for(local i = start; i < end - 2; i++){
57+ cpu_write(d, 0xa000, i);
58+ cpu_program(d, 0xa000, cpu_banksize);
59+ }
60+ cpu_program(d, 0xc000, cpu_banksize * 2);
61+}
62+
63+function vrc4_ppu_transfer(d, start, end, ppu_banksize, r0, r1)
64+{
65+ for(local i = start; i < end; i += 4){
66+ ppu_bank_set(d, 0xd000, i | 0, i | 1, r0, r1);
67+ ppu_bank_set(d, 0xe000, i | 2, i | 3, r0, r1);
68+ ppu_program(d, 0x1000, ppu_banksize * 4);
69+ }
70+}
--- /dev/null
+++ b/client/trunk/anago/vrc4a.ad
@@ -0,0 +1,21 @@
1+board <- {
2+ mappernum = 21, ppu_ramfind = false, vram_mirrorfind = false,
3+ cpu_rom = {
4+ size_base = 2 * mega, size_max = 2 * mega,
5+ banksize = 0x2000
6+ },
7+ ppu_rom = {
8+ size_base = 1 * mega, size_max = 2 * mega,
9+ banksize = 0x2000 / 8,
10+ }
11+};
12+dofile("vrc4.ai");
13+function cpu_dump(d, pagesize, banksize)
14+{
15+ vrc4_cpu_dump(d, pagesize, banksize, 1, 2);
16+}
17+
18+function ppu_dump(d, pagesize, banksize)
19+{
20+ vrc4_ppu_dump(d, pagesize, banksize, 1, 2);
21+}
--- /dev/null
+++ b/client/trunk/anago/vrc4b.af
@@ -0,0 +1,45 @@
1+board <- {
2+ mappernum = 25, ppu_ramfind = false, vram_mirrorfind = false
3+ cpu_rom = {
4+ size_base = 1 * mega, size_max = 2 * mega,
5+ banksize = 0x2000
6+ },
7+ ppu_rom = {
8+ size_base = 1 * mega, size_max = 2 * mega,
9+ banksize = 0x2000 / 8
10+ }
11+};
12+dofile("vrc4.ai");
13+function cpu_dump(d, pagesize, banksize)
14+{
15+ vrc4_cpu_dump(d, pagesize, banksize, 1, 0);
16+}
17+
18+function ppu_dump(d, pagesize, banksize)
19+{
20+ vrc4_ppu_dump(d, pagesize, banksize, 1, 0);
21+}
22+
23+/*
24+VRC4b FLASH MEMORY WRITE
25+generic CPU memory bank
26+cpu address|rom address |page|task
27+$8000-$9fff|0x02000-0x03fff|1 |write 0x2aaa
28+$a000-$bfff|n * 0x2000 |n |write area
29+$c000-$dfff|末尾-1 |fix |write 0x5555
30+$e000-$efff|末尾 |fix |boot area, 未使用
31+PPU memory bank
32+ppu address|rom address |page|task
33+$0000-$04ff|0x02800-0x027ff|0x0a|write (0x2aaa & 0x03ff) + 0
34+$0400-$07ff|0x05400-0x057ff|0x15|write (0x5555 & 0x03ff) + 0x400
35+$1000-$1fff|n * 0x1000 |n |write area
36+*/
37+function program_initalize(d, cpu_banksize, ppu_banksize)
38+{
39+ vrc4_program_initialize(d, cpu_banksize, ppu_banksize, 1, 0)
40+}
41+
42+function ppu_transfer(d, start, end, ppu_banksize)
43+{
44+ vrc4_ppu_transfer(d, start, end, ppu_banksize, 1, 0);
45+}
--- /dev/null
+++ b/client/trunk/anago/vrc4c.ag
@@ -0,0 +1,41 @@
1+board <- {
2+ mappernum = 21, ppu_ramfind = false, vram_mirrorfind = false
3+ cpu_rom = {
4+ size_base = 2 * mega, size_max = 2 * mega,
5+ banksize = 0x2000
6+ },
7+ cpu_ram = {
8+ size_base = 0x2000, size_max = 0x2000,
9+ banksize = 0x2000
10+ },
11+ ppu_rom = {
12+ size_base = 2 * mega, size_max = 2 * mega,
13+ banksize = 0x2000 / 8
14+ }
15+};
16+dofile("vrc4.ai");
17+function cpu_dump(d, pagesize, banksize)
18+{
19+ vrc4_cpu_dump(d, pagesize, banksize, 6, 7);
20+}
21+
22+function ppu_dump(d, pagesize, banksize)
23+{
24+ vrc4_ppu_dump(d, pagesize, banksize, 6, 7);
25+}
26+
27+//RC857 cartridge does not use workram register control
28+function cpu_ram_access(d, pagesize, banksize)
29+{
30+ cpu_ramrw(d, 0x6000, banksize);
31+}
32+
33+function program_initalize(d, cpu_banksize, ppu_banksize)
34+{
35+ vrc4_program_initialize(d, cpu_banksize, ppu_banksize, 6, 7)
36+}
37+
38+function ppu_transfer(d, start, end, ppu_banksize)
39+{
40+ vrc4_ppu_transfer(d, start, end, ppu_banksize, 6, 7);
41+}
--- /dev/null
+++ b/client/trunk/anago/vrc4d.ad
@@ -0,0 +1,22 @@
1+board <- {
2+ mappernum = 25,
3+ cpu_rom = {
4+ size_base = 2 * mega, size_max = 2 * mega,
5+ banksize = 0x2000
6+ },
7+ ppu_rom = {
8+ size_base = 2 * mega, size_max = 2 * mega,
9+ banksize = 0x2000 / 8
10+ },
11+ ppu_ramfind = false, vram_mirrorfind = false
12+};
13+dofile("vrc4.ai");
14+function cpu_dump(d, pagesize, banksize)
15+{
16+ vrc4_cpu_dump(d, pagesize, banksize, 3, 2);
17+}
18+
19+function ppu_dump(d, pagesize, banksize)
20+{
21+ vrc4_ppu_dump(d, pagesize, banksize, 3, 2);
22+}
--- /dev/null
+++ b/client/trunk/anago/vrc6b.af
@@ -0,0 +1,75 @@
1+/*VRC6 type B/351949A/address bus A0=R1, A1=R0
2+CPU memory bank
3+cpu address|rom address |page|task
4+$8000-$bfff|n * 0x4000 |even|write area + write 0x2aaa
5+$c000-$dfff|0x04000-0x05fff|2 |write 0x5555
6+-------------------------------------
7+$8000-$bfff|n * 0x4000 |odd |write area + write 0x5555
8+$c000-$dfff|0x02000-0x03fff|1 |write 0x2aaa
9+$e000-$efff|末尾 |fix |boot area, 未使用
10+
11+PPU memory bank
12+ppu address|rom address |page|task
13+$0000-$03ff|0x02800-0x02bff|0x0a|write (0x2aaa & 0x03ff) + 0
14+$0400-$07ff|0x05400-0x057ff|0x15|write (0x5555 & 0x03ff) + 0x400
15+$1000-$1fff|n * 0x1000 |n |write area*/
16+board <- {
17+ mappernum = 26, vram_mirrorfind = false,
18+ cpu = {banksize = 0x4000, maxsize = 2 * mega},
19+ ppu = {banksize = 0x0400, maxsize = 2 * mega},
20+}
21+function cpubank_even_set(d, bank, cpu_banksize)
22+{
23+ cpu_command(d, 0x2aaa, 0x8000, cpu_banksize);
24+ cpu_command(d, 0x5555, 0xc000, 0x2000);
25+ cpu_write(d, 0x8000, bank)
26+ cpu_write(d, 0xc000, 2)
27+}
28+function initalize(d, cpu_banksize, ppu_banksize)
29+{
30+ cpubank_even_set(d, 0, cpu_banksize);
31+ cpu_command(d, 0, 0x8000, cpu_banksize);
32+
33+ ppu_command(d, 0x2aaa, 0, ppu_banksize);
34+ ppu_command(d, 0x5555, 0x0400, ppu_banksize);
35+ ppu_command(d, 0, 0x0800, ppu_banksize);
36+
37+ cpu_write(d, 0xb003, 0); //work ram disable
38+ cpu_write(d, 0xd000, 0x0a);
39+ cpu_write(d, 0xd002, 0x15);
40+ cpu_write(d, 0xd001, 0x00);
41+ cpu_write(d, 0xd003, 0x00);
42+}
43+function cpu_transfer(d, start, end, cpu_banksize)
44+{
45+ local i;
46+ for(i = start; i < end - 2; i += 2){
47+ cpubank_even_set(d, i, cpu_banksize);
48+ cpu_program(d, 0x8000, cpu_banksize);
49+
50+ cpu_command(d, 0x5555, 0x8000, cpu_banksize);
51+ cpu_command(d, 0x2aaa, 0xc000, 0x2000);
52+ cpu_write(d, 0x8000, i | 1)
53+ cpu_write(d, 0xc000, 1)
54+ cpu_program(d, 0x8000, cpu_banksize);
55+ }
56+ cpubank_even_set(d, i, cpu_banksize);
57+ cpu_program(d, 0x8000, cpu_banksize);
58+
59+ cpu_command(d, 0x5555, 0x8000, cpu_banksize);
60+ cpu_command(d, 0x2aaa, 0xc000, 0x2000);
61+ cpu_write(d, 0x8000, i | 1)
62+ cpu_write(d, 0xc000, 1)
63+ cpu_program(d, 0x8000, cpu_banksize);
64+}
65+
66+function ppu_transfer(d, start, end, ppu_banksize)
67+{
68+ for(local i = start; i < end; i += 4){
69+ cpu_write(d, 0xe000, i | 0);
70+ cpu_write(d, 0xe002, i | 1);
71+ cpu_write(d, 0xe001, i | 2);
72+ cpu_write(d, 0xe003, i | 3);
73+ ppu_program(d, 0x1000, ppu_banksize * 4);
74+ }
75+}
--- /dev/null
+++ b/client/trunk/anago/vrc7.ag
@@ -0,0 +1,69 @@
1+/*VRC7 FLASH MEMORY WRITE
2+generic CPU memory bank
3+cpu address|rom address |page|task
4+$8000-$9fff|0x02000-0x03fff|1 |write (0x2aaa & 0x1fff) + 0x8000
5+$a000-$bfff|0x04000-0x05fff|2 |write (0x5555 & 0x1fff) + 0xa000
6+$c000-$dfff|n * 0x2000 |n |write area
7+$e000-$efff|末尾 |fix |boot area, 未使用*/
8+board <- {
9+ mappernum = 85, vram_mirrorfind = false, ppu_ramfind = true,
10+ cpu_rom = {banksize = 0x2000, size_max = 4 * mega, size_base = 1 * mega},
11+ cpu_ram = {banksize = 0x2000, size_max = 0x2000, size_base = 0x2000},
12+ ppu_rom = {banksize = 0x2000 / 8, size_max = 2 * mega, size_base = 1* mega}
13+};
14+function cpu_dump(d, pagesize, banksize)
15+{
16+ for(local i = 0; i < pagesize - 2; i += 2){
17+ cpu_write(d, 0x8000, i);
18+ cpu_write(d, 0x8018, i | 1);
19+ cpu_read(d, 0x8000, banksize * 2);
20+ }
21+ cpu_write(d, 0x9000, 0x3e);
22+ cpu_read(d, 0xc000, banksize * 2);
23+}
24+
25+function ppu_dump(d, pagesize, banksize)
26+{
27+ cpu_write(d, 0xa000, 0);
28+ for(local i = 0; i < pagesize; i += 8){
29+ local t = i;
30+ for(local j = 0xa000; j < 0xe000; j += 0x1000){
31+ cpu_write(d, j, t++);
32+ cpu_write(d, j+0x18, t++);
33+ }
34+ ppu_read(d, 0, banksize * 8);
35+ }
36+}
37+
38+function cpu_ram_access(d, pagesize, banksize)
39+{
40+ cpu_write(d, 0xe000, 0x80);
41+ cpu_ramrw(d, 0x6000, banksize);
42+ cpu_write(d, 0xe000, 0x00);
43+}
44+
45+/*
46+this is RC851/352402 style. RV051/353429 style is not supported.
47+352402: Program ROM/ Charcter RAM/ Backup RAM/ R1 = A5, R0 = A4/ Extra Sound
48+353429: Program ROM/ Charcter ROM/ R1 = A3, R0 = ?
49+*/
50+function initalize(d, cpu_banksize, ppu_banksize)
51+{
52+ cpu_command(d, 0, 0xc000, cpu_banksize);
53+ cpu_command(d, 0x2aaa, 0x8000, cpu_banksize);
54+ cpu_command(d, 0x5555, 0xa000, cpu_banksize);
55+ cpu_write(d, 0x8000, 1);
56+ cpu_write(d, 0x8010, 2);
57+ cpu_write(d, 0x9000, 0);
58+}
59+function cpu_transfer(d, start, end, banksize)
60+{
61+ for(local i = start; i < end - 1; i += 1){
62+ cpu_write(d, 0x9000, i);
63+ cpu_program(d, 0xc000, banksize);
64+ }
65+ cpu_program(d, 0xe000, banksize);
66+}
67+function ppu_transfer(d, start, end, size)
68+{
69+}
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