external/drm_gralloc
リビジョン | b65a3f83ccf8d17cea46fe5af1bc348ad5d4467f (tree) |
---|---|
日時 | 2011-10-27 19:40:45 |
作者 | Chia-I Wu <olvaffe@gmai...> |
コミッター | Chia-I Wu |
add support for YUV formats
@@ -61,8 +61,15 @@ static inline int gralloc_drm_get_bpp(int format) | ||
61 | 61 | case HAL_PIXEL_FORMAT_RGB_565: |
62 | 62 | case HAL_PIXEL_FORMAT_RGBA_5551: |
63 | 63 | case HAL_PIXEL_FORMAT_RGBA_4444: |
64 | + case HAL_PIXEL_FORMAT_YCbCr_422_I: | |
64 | 65 | bpp = 2; |
65 | 66 | break; |
67 | + /* planar; only Y is considered */ | |
68 | + case HAL_PIXEL_FORMAT_YV12: | |
69 | + case HAL_PIXEL_FORMAT_YCbCr_422_SP: | |
70 | + case HAL_PIXEL_FORMAT_YCrCb_420_SP: | |
71 | + bpp = 1; | |
72 | + break; | |
66 | 73 | default: |
67 | 74 | bpp = 0; |
68 | 75 | break; |
@@ -71,6 +78,37 @@ static inline int gralloc_drm_get_bpp(int format) | ||
71 | 78 | return bpp; |
72 | 79 | } |
73 | 80 | |
81 | +static inline void gralloc_drm_align_geometry(int format, int *width, int *height) | |
82 | +{ | |
83 | + int align_w = 1, align_h = 1, extra_height_div = 0; | |
84 | + | |
85 | + switch (format) { | |
86 | + case HAL_PIXEL_FORMAT_YV12: | |
87 | + align_w = 32; | |
88 | + align_h = 2; | |
89 | + extra_height_div = 2; | |
90 | + break; | |
91 | + case HAL_PIXEL_FORMAT_YCbCr_422_SP: | |
92 | + align_w = 2; | |
93 | + extra_height_div = 1; | |
94 | + break; | |
95 | + case HAL_PIXEL_FORMAT_YCrCb_420_SP: | |
96 | + align_w = 2; | |
97 | + align_h = 2; | |
98 | + extra_height_div = 2; | |
99 | + break; | |
100 | + case HAL_PIXEL_FORMAT_YCbCr_422_I: | |
101 | + align_w = 2; | |
102 | + break; | |
103 | + } | |
104 | + | |
105 | + *width = (*width + align_w - 1) & ~(align_w - 1); | |
106 | + *height = (*height + align_h - 1) & ~(align_h - 1); | |
107 | + | |
108 | + if (extra_height_div) | |
109 | + *height += *height / extra_height_div; | |
110 | +} | |
111 | + | |
74 | 112 | int gralloc_drm_handle_register(buffer_handle_t handle, struct gralloc_drm_t *drm); |
75 | 113 | int gralloc_drm_handle_unregister(buffer_handle_t handle); |
76 | 114 |
@@ -309,6 +309,11 @@ static drm_intel_bo *alloc_ibo(struct intel_info *info, | ||
309 | 309 | return NULL; |
310 | 310 | } |
311 | 311 | |
312 | + aligned_width = handle->width; | |
313 | + aligned_height = handle->height; | |
314 | + gralloc_drm_align_geometry(handle->format, | |
315 | + &aligned_width, &aligned_height); | |
316 | + | |
312 | 317 | if (handle->usage & GRALLOC_USAGE_HW_FB) { |
313 | 318 | unsigned long max_stride; |
314 | 319 |
@@ -319,8 +324,7 @@ static drm_intel_bo *alloc_ibo(struct intel_info *info, | ||
319 | 324 | max_stride /= 2; |
320 | 325 | |
321 | 326 | name = "gralloc-fb"; |
322 | - aligned_width = (handle->width + 63) & ~63; | |
323 | - aligned_height = handle->height; | |
327 | + aligned_width = (aligned_width + 63) & ~63; | |
324 | 328 | flags = BO_ALLOC_FOR_RENDER; |
325 | 329 | |
326 | 330 | *tiling = I915_TILING_X; |
@@ -368,13 +372,11 @@ static drm_intel_bo *alloc_ibo(struct intel_info *info, | ||
368 | 372 | if (handle->usage & GRALLOC_USAGE_HW_TEXTURE) { |
369 | 373 | name = "gralloc-texture"; |
370 | 374 | /* see 2D texture layout of DRI drivers */ |
371 | - aligned_width = (handle->width + 3) & ~3; | |
372 | - aligned_height = (handle->height + 1) & ~1; | |
375 | + aligned_width = (aligned_width + 3) & ~3; | |
376 | + aligned_height = (aligned_height + 1) & ~1; | |
373 | 377 | } |
374 | 378 | else { |
375 | 379 | name = "gralloc-buffer"; |
376 | - aligned_width = handle->width; | |
377 | - aligned_height = handle->height; | |
378 | 380 | } |
379 | 381 | |
380 | 382 | if (handle->usage & GRALLOC_USAGE_HW_RENDER) |
@@ -198,9 +198,13 @@ nouveau_alloc(struct gralloc_drm_drv_t *drv, struct gralloc_drm_handle_t *handle | ||
198 | 198 | } |
199 | 199 | } |
200 | 200 | else { |
201 | - int pitch; | |
201 | + int width, height, pitch; | |
202 | 202 | |
203 | - nb->bo = alloc_bo(info, handle->width, handle->height, | |
203 | + width = handle->width; | |
204 | + height = handle->height; | |
205 | + gralloc_drm_align_geometry(handle->format, &width, &height); | |
206 | + | |
207 | + nb->bo = alloc_bo(info, width, height, | |
204 | 208 | cpp, handle->usage, &pitch); |
205 | 209 | if (!nb->bo) { |
206 | 210 | LOGE("failed to allocate nouveau bo %dx%dx%d", |
@@ -76,6 +76,9 @@ static enum pipe_format get_pipe_format(int format) | ||
76 | 76 | break; |
77 | 77 | case HAL_PIXEL_FORMAT_RGBA_5551: |
78 | 78 | case HAL_PIXEL_FORMAT_RGBA_4444: |
79 | + case HAL_PIXEL_FORMAT_YV12: | |
80 | + case HAL_PIXEL_FORMAT_YCbCr_422_SP: | |
81 | + case HAL_PIXEL_FORMAT_YCrCb_420_SP: | |
79 | 82 | default: |
80 | 83 | fmt = PIPE_FORMAT_NONE; |
81 | 84 | break; |
@@ -201,16 +201,17 @@ static struct radeon_bo *radeon_alloc(struct radeon_info *info, | ||
201 | 201 | tiling = radeon_get_tiling(info, handle); |
202 | 202 | domain = RADEON_GEM_DOMAIN_VRAM; |
203 | 203 | |
204 | + aligned_width = handle->width; | |
205 | + aligned_height = handle->height; | |
206 | + gralloc_drm_align_geometry(handle->format, | |
207 | + &aligned_width, &aligned_height); | |
208 | + | |
204 | 209 | if (handle->usage & (GRALLOC_USAGE_HW_FB | GRALLOC_USAGE_HW_TEXTURE)) { |
205 | - aligned_width = ALIGN(handle->width, | |
210 | + aligned_width = ALIGN(aligned_width, | |
206 | 211 | radeon_get_pitch_align(info, cpp, tiling)); |
207 | - aligned_height = ALIGN(handle->height, | |
212 | + aligned_height = ALIGN(aligned_height, | |
208 | 213 | radeon_get_height_align(info, tiling)); |
209 | 214 | } |
210 | - else { | |
211 | - aligned_width = handle->width; | |
212 | - aligned_height = handle->height; | |
213 | - } | |
214 | 215 | |
215 | 216 | if (!(handle->usage & (GRALLOC_USAGE_HW_FB | |
216 | 217 | GRALLOC_USAGE_HW_RENDER)) && |